--- /sys/src/9/pc/ethervt6105m.c	Mon Apr 28 22:46:36 2014
+++ /sys/src/9/pc/ethervt6105m.c	Fri May  2 21:32:42 2014
@@ -1,13 +1,10 @@
 /*
  * VIA VT6105M Fast Ethernet Controller (Rhine III).
  * To do:
- *	cache-line size alignments - done
- *	reduce tx interrupts - done
  *	reorganise initialisation/shutdown/reset
  *	adjust Tx FIFO threshold on underflow - untested
  *	why does the link status never cause an interrupt?
  *	use the lproc as a periodic timer for stalls, etc.
- *	checksum offload - done
  *	take non-HW stuff out of descriptor for 64-bit
  *	cleanliness
  *	why does the receive buffer alloc have a +3?
@@ -286,11 +283,10 @@
 	Crcsz		= 4,
 	Bslop		= 48,
 	Rdbsz		= ETHERMAXTU+Crcsz+Bslop,
+	Maxus		= 1000000,  /* Soekris 5501s take a while to reset */
 
 	Nrxstats	= 8,
 	Ntxstats	= 9,
-
-	Txcopy		= 128,
 };
 
 typedef struct Ctlr Ctlr;
@@ -978,12 +974,12 @@
 		csr16w(ctlr, Miidata, data);
 	csr8w(ctlr, Miicr, cmd);
 
-	for(timeo = 0; timeo < 10000; timeo++){
+	for(timeo = 0; timeo < Maxus; timeo++){
 		if(!(csr8r(ctlr, Miicr) & cmd))
 			break;
 		microdelay(1);
 	}
-	if(timeo >= 10000)
+	if(timeo >= Maxus)
 		return -1;
 
 	if(cmd == Wcmd)
@@ -1029,13 +1025,12 @@
 	 */
 	csr16w(ctlr, Cr, Stop);
 	csr16w(ctlr, Cr, Stop|Sfrst);
-	/* limit used to be 10000, but that wasn't enough for our Soekris 5501s */
-	for(timeo = 0; timeo < 100000; timeo++){
+	for(timeo = 0; timeo < Maxus; timeo++){
 		if(!(csr16r(ctlr, Cr) & Sfrst))
 			break;
 		microdelay(1);
 	}
-	if(timeo >= 1000)
+	if(timeo >= Maxus)
 		return -1;
 
 	return 0;
@@ -1064,13 +1059,12 @@
 	 */
 	r = csr8r(ctlr, Eecsr);
 	csr8w(ctlr, Eecsr, Autold|r);
-	/* limit used to be 100, but that wasn't enough for our Soekris 5501s */
-	for(timeo = 0; timeo < 1000000; timeo++){
+	for(timeo = 0; timeo < Maxus; timeo++){
 		if(!(csr8r(ctlr, Cr) & Autold))
 			break;
 		microdelay(1);
 	}
-	if(timeo >= 1000000)
+	if(timeo >= Maxus)
 		return -1;
 
 	for(i = 0; i < Eaddrlen; i++)