Reset Wake-on-LAN/power management registers on chip reset.  This gets my VIA Rhine II (PCI rev id 0x71) working.  Without this patch the card is not initialized properly and the MII init fails.

The source for this extra init behavior is gPXE's via-rhine.c and Linux 2.6.24's via-rhine.c.  Both do basically the same thing with the power management registers when setting up the card.

Reference: /n/sources/patch/applied/vt6102pwr
Date: Sun Apr 20 22:58:33 CES 2008
Signed-off-by: stefanha@gmail.com

--- /sys/src/9/pc/ethervt6102.c	Sun Apr 20 22:55:24 2008
+++ /sys/src/9/pc/ethervt6102.c	Sun Apr 20 22:55:18 2008
@@ -40,6 +40,10 @@
 	Miiadr		= 0x71,		/* MII Address */
 	Miidata		= 0x72,		/* MII Data */
 	Eecsr		= 0x74,		/* EEPROM Control and Status */
+	Sticky		= 0x83,
+	Wolcrclr	= 0xA4,
+	Wolcgclr	= 0xA7,
+	Pwrcsrclr	= 0xAC,
 };
 
 enum {					/* Rcr */
@@ -837,7 +841,23 @@
 static int
 vt6102detach(Ctlr* ctlr)
 {
-	int timeo;
+	int revid, timeo;
+
+	/*
+	 * Reset power management registers.
+	 */
+	revid = pcicfgr8(ctlr->pcidev, PciRID);
+	if(revid >= 0x40){
+		/* Set power state D0. */
+		csr8w(ctlr, Sticky, csr8r(ctlr, Sticky) & 0xFC);
+
+		/* Disable force PME-enable. */
+		csr8w(ctlr, Wolcgclr, 0x80);
+
+		/* Clear WOL config and status bits. */
+		csr8w(ctlr, Wolcrclr, 0xFF);
+		csr8w(ctlr, Pwrcsrclr, 0xFF);
+	}
 
 	/*
 	 * Soft reset the controller.