1. print model number when coming up. 2. remove cache line size stuff. pcie doesn't have a cache-line size, at least in the sense it was being used. 3. properly set the size for non-ip packets. 4. i82563cleanup. revert to seperate if's. the tweaks are somewhat independent of model and might apply to one some or many models. 5. revert 32bit wide registers to eight places. it's easier for me to keep track of the bits. 6. remove a bunch of depricated enums. Reference: /n/sources/patch/applied/82563upd Date: Wed Oct 10 20:26:28 CES 2007 Signed-off-by: quanstro@quanstro.net --- /sys/src/9/pc/ether82563.c Wed Oct 10 20:18:40 2007 +++ /sys/src/9/pc/ether82563.c Wed Oct 10 20:18:31 2007 @@ -123,9 +123,9 @@ Slu = 1<<6, /* Set Link Up */ SspeedMASK = 3<<8, /* Speed Selection */ SspeedSHIFT = 8, - Sspeed10 = 0x0000, /* 10Mb/s */ - Sspeed100 = 0x0100, /* 100Mb/s */ - Sspeed1000 = 0x0200, /* 1000Mb/s */ + Sspeed10 = 0x00000000, /* 10Mb/s */ + Sspeed100 = 0x00000100, /* 100Mb/s */ + Sspeed1000 = 0x00000200, /* 1000Mb/s */ Frcspd = 1<<11, /* Force Speed */ Frcdplx = 1<<12, /* Force Duplex */ SwdpinsloMASK = 0x003C0000, /* Software Defined Pins - lo nibble */ @@ -144,36 +144,13 @@ Lanid = 3<<2, /* mask for Lan ID. Txoff = 1<<4, /* Transmission Paused */ Tbimode = 1<<5, /* TBI Mode Indication */ - SpeedMASK = 0x00C0, - Speed10 = 0x0000, /* 10Mb/s */ - Speed100 = 0x0040, /* 100Mb/s */ - Speed1000 = 0x0080, /* 1000Mb/s */ Phyra = 1<<10, /* PHY Reset Asserted */ GIOme = 1<<19, /* GIO Master Enable Status */ }; -enum { /* Ctrl and Status */ - Fd = 0x0001, /* Full-Duplex */ - AsdvMASK = 0x0300, - Asdv10 = 0x0000, /* 10Mb/s */ - Asdv100 = 0x0100, /* 100Mb/s */ - Asdv1000 = 0x0200, /* 1000Mb/s */ -}; - -enum { /* Eec */ - Sk = 1<<0, /* Clock input to the EEPROM */ - Cs = 1<<1, /* Chip Select */ - Di = 1<<2, /* Data Input to the EEPROM */ - Do = 1<<3, /* Data Output from the EEPROM */ - Areq = 1<<6, /* EEPROM Access Request */ - Agnt = 1<<7, /* EEPROM Access Grant */ -}; - enum { /* Eerd */ - Ee_start = 1<<0, /* Start Read */ - Ee_done = 1<<1, /* Read done */ - Ee_addr = 0xfff8<<2, /* Read address [15:2] */ - Ee_data = 0xffff<<16, /* Read Data; Data returned from eeprom/nvm */ + EEstart = 1<<0, /* Start Read */ + EEdone = 1<<1, /* Read done */ }; enum { /* Ctrlext */ @@ -194,7 +171,7 @@ }; enum { /* Mdic */ - MDIdMASK = 0xFFFF, /* Data */ + MDIdMASK = 0x0000FFFF, /* Data */ MDIdSHIFT = 0, MDIrMASK = 0x001F0000, /* PHY Register Address */ MDIrSHIFT = 16, @@ -216,58 +193,58 @@ }; enum { /* Icr, Ics, Ims, Imc */ - Txdw = 0x0001, /* Transmit Descriptor Written Back */ - Txqe = 0x0002, /* Transmit Queue Empty */ - Lsc = 0x0004, /* Link Status Change */ - Rxseq = 0x0008, /* Receive Sequence Error */ - Rxdmt0 = 0x0010, /* Rdesc Minimum Threshold Reached */ - Rxo = 0x0040, /* Receiver Overrun */ - Rxt0 = 0x0080, /* Receiver Timer Interrupt */ - Mdac = 0x0200, /* MDIO Access Completed */ - Rxcfg = 0x0400, /* Receiving /C/ ordered sets */ - Gpi0 = 0x0800, /* General Purpose Interrupts */ - Gpi1 = 0x1000, - Gpi2 = 0x2000, - Gpi3 = 0x4000, + Txdw = 0x00000001, /* Transmit Descriptor Written Back */ + Txqe = 0x00000002, /* Transmit Queue Empty */ + Lsc = 0x00000004, /* Link Status Change */ + Rxseq = 0x00000008, /* Receive Sequence Error */ + Rxdmt0 = 0x00000010, /* Rdesc Minimum Threshold Reached */ + Rxo = 0x00000040, /* Receiver Overrun */ + Rxt0 = 0x00000080, /* Receiver Timer Interrupt */ + Mdac = 0x00000200, /* MDIO Access Completed */ + Rxcfg = 0x00000400, /* Receiving /C/ ordered sets */ + Gpi0 = 0x00000800, /* General Purpose Interrupts */ + Gpi1 = 0x00001000, + Gpi2 = 0x00002000, + Gpi3 = 0x00004000, Ack = 0x00020000, /* Receive ACK frame */ }; enum { /* Txcw */ - TxcwFd = 0x0020, /* Full Duplex */ - TxcwHd = 0x0040, /* Half Duplex */ - TxcwPauseMASK = 0x0180, /* Pause */ + TxcwFd = 0x00000020, /* Full Duplex */ + TxcwHd = 0x00000040, /* Half Duplex */ + TxcwPauseMASK = 0x00000180, /* Pause */ TxcwPauseSHIFT = 7, TxcwPs = 1<type == i82573) csr32w(ctlr, Ert, 1024/8); - else if(ctlr->type == i82566) + + if(ctlr->type == i82566) csr32w(ctlr, Pbs, 16); csr32w(ctlr, Rdbal, PCIWADDR(ctlr->rdba)); @@ -996,6 +972,7 @@ if (bp = ctlr->rb[rdh]) { if((rd->status & Reop) && rd->errors == 0){ bp->wp += rd->length; + bp->lim = bp->wp; /* lie like a dog. */ if(!(rd->status & Ixsm)){ ctlr->ixsm++; if(rd->status & Ipcs){ @@ -1016,7 +993,6 @@ } bp->checksum = rd->checksum; bp->flag |= Bpktck; - bp->lim = bp->wp; /* lie like a dog. */ } etheriq(edev, bp, 1); } else @@ -1057,7 +1033,7 @@ } if((phy & (MDIe|MDIready)) != MDIready) return ~0; - return (ushort)phy; + return phy&0xffff; } static uint @@ -1108,7 +1084,7 @@ break; case i82571: case i82572: - i = (i-1) & 3; + i = i-1 & 3; break; } @@ -1152,14 +1128,13 @@ ctlr->nrd = Nrd; ctlr->ntd = Ntd; - ctlr->alloc = mallocz(ctlr->nrd*sizeof(Rd) + ctlr->ntd*sizeof(Td) + 255, - 1); + ctlr->alloc = malloc(ctlr->nrd*sizeof(Rd)+ctlr->ntd*sizeof(Td) + 255); if(ctlr->alloc == nil){ qunlock(&ctlr->alock); return; } ctlr->rdba = (Rd*)ROUNDUP((ulong)ctlr->alloc, 256); - ctlr->tdba = (Td*)(ctlr->rdba+ ctlr->nrd); + ctlr->tdba = (Td*)(ctlr->rdba + ctlr->nrd); ctlr->rb = malloc(ctlr->nrd * sizeof(Block*)); ctlr->tb = malloc(ctlr->ntd * sizeof(Block*)); @@ -1188,13 +1163,13 @@ freeb(bp); } - snprint(name, KNAMELEN, "#l%dlproc", edev->ctlrno); + snprint(name, sizeof name, "#l%dl", edev->ctlrno); kproc(name, i82563lproc, edev); - snprint(name, KNAMELEN, "#l%drproc", edev->ctlrno); + snprint(name, sizeof name, "#l%dr", edev->ctlrno); kproc(name, i82563rproc, edev); - snprint(name, KNAMELEN, "#l%dtproc", edev->ctlrno); + snprint(name, sizeof name, "#l%dt", edev->ctlrno); kproc(name, i82563tproc, edev); i82563txinit(ctlr); @@ -1252,7 +1227,7 @@ ctlr->type == i82572)){ ctlr->pba = csr32r(ctlr, Pba); r = ctlr->pba >> 16; - r += (ushort)ctlr->pba; + r += ctlr->pba&0xffff; r >>= 1; csr32w(ctlr, Pba, r); } else if(ctlr->type == i82573 && ctlr->rbsz > 1514) @@ -1319,8 +1294,8 @@ static ushort eeread(Ctlr* ctlr, int adr) { - csr32w(ctlr, Eerd, Ee_start | adr << 2); - while ((csr32r(ctlr, Eerd) & Ee_done) == 0) + csr32w(ctlr, Eerd, EEstart | adr << 2); + while ((csr32r(ctlr, Eerd) & EEdone) == 0) ; return csr32r(ctlr, Eerd) >> 16; } @@ -1341,7 +1316,7 @@ } static int -i82563reset(Ctlr* ctlr) +i82563reset(Ctlr *ctlr) { int i, r; @@ -1383,7 +1358,7 @@ static void i82563pci(void) { - int cls, type; + int type; ulong io; void *mem; Pcidev *p; @@ -1424,26 +1399,11 @@ p->mem[0].bar); continue; } - cls = pcicfgr8(p, PciCLS); - switch(cls){ - default: - print("%s: unexpected CLS %d\n", - tname[type], cls*4); - break; - case 0x00: - case 0xFF: - print("%s: unusable CLS\n", tname[type]); - continue; - case 0x08: - case 0x10: - break; - } ctlr = malloc(sizeof(Ctlr)); ctlr->port = io; ctlr->pcidev = p; ctlr->type = type; ctlr->rbsz = rbtab[type]; - ctlr->cls = cls*4; ctlr->nic = mem; if(i82563reset(ctlr)){ @@ -1549,11 +1509,11 @@ void ether82563link(void) { - addethercard("igbepcie", anypnp); /* recognise lots of model numbers for debugging assistance */ addethercard("i82563", i82563pnp); addethercard("i82566", i82566pnp); addethercard("i82571", i82571pnp); addethercard("i82572", i82572pnp); addethercard("i82573", i82573pnp); + addethercard("igbepcie", anypnp); }