# HG changeset patch
# User Noah Evans <npe@plan9.bell-labs.com>
# Date 1307445539 0
# Node ID 85df9273b94554d3563509ab3cfcdc63001e2e26
# Parent  ddaa629716d50dce42e334f51fbcbbf92c70c3f4
paper modifications and more performance counter code

diff -r ddaa629716d5 -r 85df9273b945 doc/papers/nix/nix.ms
--- a/doc/papers/nix/nix.ms	Tue Jun 07 09:08:27 2011 +0000
+++ b/doc/papers/nix/nix.ms	Tue Jun 07 11:18:59 2011 +0000
@@ -13,7 +13,9 @@
 Francisco J. Ballesteros
 Gorka Guardiola
 Enrique Soriano
-(want your name here? Just ask!)
+Jim McKie
+Charles Forsyth
+Noah Evans
 .AB
 This paper describes NIX, a prototype operating system for future
 manycore CPUs.  NIX features a heterogeneous CPU model and a change
@@ -52,7 +54,7 @@
 However, in the era of multi-core and many-core machines, we believe that
 we could get rid of the entire operating system kernel. We advocate for a
 null-kernel or zero-kernel approach, where applications are assigned to
-cores without no OS interference; that is, without an operating system kernel.
+cores with no OS interference; that is, without an operating system kernel.
 Following this idea, we have built NIX.
 .PP
 NIX is a new operating system, evolving from a traditional operating
@@ -74,7 +76,7 @@
 possible future direction.
 .PP
 NIX uses a messaging protocol between cores based on shared-memory
-active messages. A active message sends not just references to data,
+active messages. An active message sends not just references to data,
 but also to code.
 The protocol uses a shared memory data structure,
 containing cache-aligned fields.  In particular, it contains
@@ -98,14 +100,14 @@
 sheet designs.  NIX thus begins life with a working kernel and full
 set of userland code.
 .PP
-The idea to keep a standard time-sharing kernel as it is now, but be
+The idea is to keep a standard time-sharing kernel as it is now, but to be
 able to exploit other cores for either user or kernel intensive
 processes.  In the worst case, the time-sharing kernel will be able to
 work as it does now.  In the best case, applications will be able to
 run as fast as permitted by the raw hardware.
 .PP
 NIX derives from Plan 9 from Bell Labs.
-Source code, compiled for Plan 9, also work son NIX.  We make an even
+Source code, compiled for Plan 9, also works on NIX.  We make an even
 stronger guarantee: if a binary worked on Plan 9, it will work on NIX.
 .PP
 NIX partitions cores by function, hence implementing a type of
@@ -128,17 +130,17 @@
 but TCs, as determined by the needs of the user. When all the cores
 are TC cores, behaviour is not different from a SMP system.
 .IP 2
-The second, AC, is an Application Core: only APs can be Application
+The second, AC, is an application core: only APs can be Application
 Cores.  Application cores run applications, in a non-preemptive mode,
 and never field interrupts. In this case, applications run as if they
 had no operating system, but they can still make system calls and
 rely on OS services as provided by other cores. But for performance,
 running on ACs is transparent to applications, unless they want to
-take control of this.
+take control of this feature.
 .IP 3
-The third, KC, is a Kernel Core.  Kernel Cores can be created under
+The third, KC, is a kernel core.  Kernel cores can be created under
 control of the TC. KCs do nothing but run OS tasks for the TC. A KC
-might, for example, run a file system.  KCs never run user mode code.
+might, for example, run a file system call.  KCs never run user mode code.
 Typical usages for KCs are to service interrupts from device drivers and
 to perform system calls requested to, otherwise overloaded, TCs.
 .LP
@@ -199,7 +201,7 @@
 Application cores. The BSP (a TC) coordinates the roles for other cores, which may change
 during time.
 .F3
-.PP
+.LP
 Therefore, there are two different types of kernel in the system: TCs and KCs
 execute the standard time-sharing kernel. ACs execute almost without a kernel,
 but for a few exception handlers and their main scheduling loop,
@@ -212,7 +214,7 @@
 Cores can change roles, again under the control of the TC. A core
 might be needed for applications, in which case NIX can direct the
 core to enter the AC command loop.  Later, the TC might instruct the core
-to exit the AC loop and re enter the group of
+to exit the AC loop and re-enter the group of
 TCs.  At present, only one core ­the BSP­ boots to become a TC; all
 other cores boot and enter the AC command loop.  This will be fixed soon.
 .NH 1
@@ -338,7 +340,7 @@
 is found on a different core, but the kernel part remains in the TC
 as a handler for system calls and traps.
 .F3
-.PP
+.LP
 Binary compatibility for processes is hence rather easy: old processes
 only run on a TC, unless the kernel decides otherwise.
 If a user makes a mistake and starts an old binary
@@ -357,12 +359,12 @@
 standard toolkit of IPC mechanisms in Plan 9, NIX includes
 two mechanisms for this purpose:
 .IP \(bu
-Optimistic user-level semaphores.
+Optimistic user-level semaphores, and
 .IP \(bu
-Tubes
+Tubes.
 .LP
 NIX semaphores use atomic increment and decrement operations,
-as found on AMD64 architectures, to update a semaphore value in
+as found on AMD64 and other architectures, to update a semaphore value in
 order to synchronize. If the operation performed in the semaphore
 may proceed without blocking (and without requiring to awake a peer
 process), it is performed by the user library without entering the kernel.
@@ -389,21 +391,22 @@
 .I semwakeup )
 to block or wake up another process, if required. Optionally, before blocking,
 .I downsem
-may spin, busy waiting for a chance to perform a down on the semaphore.
+may spin, busy waiting for a chance to perform a down on the semaphore
+without blocking.
 .PP
 .I Altsems
 is a novel operation, which tries to perform a
 .I downsem
 in one of the given semaphores. It is not known in advance in which
-semaphore will be the down operation performed. If more than one
-semaphores are ready for a down without blocking, one of them is elected
+semaphore will be the down operation performed. If several
+semaphores are ready for a down without blocking, one of them is selected
 and the down is performed; the function returns an index value indicating
 which one. If none of the downs may proceed, the operation calls the kernel
 and blocks.
 .PP
-Therefore, in the best case, a
-.I downsem
-is performed in user space, without entering the kernel, in a non-determinist way.
+Therefore, in the best case, 
+.I altsems
+performs a down in user space, without entering the kernel, in a non-determinist way.
 In the worst case, the kernel is used to await for a chance to down one of the
 semaphores. Before doing so, the operation may be configured to spin and
 busy wait for a while.
@@ -411,19 +414,17 @@
 Optimistic semaphores, as described, are used in NIX to implement
 shared memory communication channels called
 .I tubes .
-.PP
-A tube is a buffered unidirectional channel where fixed-size messages can be
+A tube is a buffered unidirectional channel. Fixed-size messages can be
 sent and received from it (but different tubes may have different message sizes).
 .PP
 The implementation is a simple producer-consumer, but, because of the
-semaphores used, is able to run at user space without entering the kernel
+semaphores used, it is able to run at user space without entering the kernel
 when sends and receives may proceed.
 .PP
 It is feasible to try to perform multiple sends and receives at the same time,
-waiting for the chance to execute one of them. This operation exploits the
-semantics and implementation of
+waiting for the chance to execute one of them. This operation exploits 
 .I altsems
-to operate at user-level if possible, and call the kernel otherwise.
+to operate at user-level if possible, calling the kernel otherwise.
 It suffices to fill an array of semaphores with either the ones representing
 messages in a tube, or the ones representing empty slots in a tube, depending
 on whether a receive or a send operation is selected. Then, calling
@@ -447,9 +448,18 @@
 pre-paging, which is interesting on its own.
 .PP
 To dispatch a process for
-execution at one AC, we use the inter core call, active message,
-mechanism.
-The figure shows the inter-core-call or ICC mechanism.
+execution at one AC we use the inter-core-call, active message,
+mechanism. This figure explains how it works:
+.PS
+boxht=.5
+right
+box "runac"
+arrow <-> dotted
+box "acsched"
+box invis "TC" with .s at 1st box.n
+box invis "AC" with .s at 2nd box.n
+.PE
+.LP
 The function
 .I acsched
 runs on ACs, as part of its start-up sequence. It sits in a tight loop spinning
@@ -469,16 +479,7 @@
 .I ready
 on the process that scheduled the function for execution.
 You think of this as a soft IPI.
-.PS
-boxht=.5
-right
-box "runac"
-arrow <-> dotted
-box "acsched"
-box invis "TC" with .s at 1st box.n
-box invis "AC" with .s at 2nd box.n
-.PE
-.LP
+.PP
 While an AC is performing an action dictated by a process in the TC,
 its
 .I Mach
diff -r ddaa629716d5 -r 85df9273b945 doc/papers/nix/nix.pdf
Binary file doc/papers/nix/nix.pdf has changed
diff -r ddaa629716d5 -r 85df9273b945 doc/papers/nix/nix.ps
--- a/doc/papers/nix/nix.ps	Tue Jun 07 09:08:27 2011 +0000
+++ b/doc/papers/nix/nix.ps	Tue Jun 07 11:18:59 2011 +0000
@@ -632,343 +632,283 @@
 (J. Ballesteros) 3020 1770 w
 (Gorka Guardiola) 2653 1900 w
 (Enrique Soriano) 2671 2030 w
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@@ -978,571 +918,590 @@
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 2 pagesetup
 11 /LucidaSansUnicode00 f
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 4 pagesetup
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 11 /LucidaSans-Demi f
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 11 /LucidaSans-Italic f
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 11 /LucidaSans-Demi f
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 cleartomark
 showpage
 saveobj restore
@@ -3314,407 +3244,443 @@
 /saveobj save def
 mark
 5 pagesetup
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 11 /LucidaSans-Italic f
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 11 /LucidaSans-Italic f
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 10 /LucidaSansUnicode00 f
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 11 /LucidaSans-Demi f
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 11 /LucidaSansUnicode22 f
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 11 /LucidaSansUnicode22 f
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 cleartomark
 showpage
 saveobj restore
@@ -3723,588 +3689,494 @@
 /saveobj save def
 mark
 6 pagesetup
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 11 /LucidaSans-Italic f
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 11 /LucidaSans-Italic f
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 11 /LucidaSans-Italic f
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 11 /LucidaSans-Italic f
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@@ -4313,444 +4185,530 @@
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 7 pagesetup
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-(up) 2353 2515 w
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-(AC) 2895 2515 w
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-(a) 1307 2645 w
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 11 /LucidaSans-Italic f
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-(.) 2371 2645 w
-(Should) 2479 2645 w
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 11 /LucidaSans-Italic f
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-(by) 5346 3201 w
-(NIX to dispatch processes to ACs, as shown:) 720 3331 w
-1926 3866 1926 3506 Dl
-1926 3506 2466 3506 Dl
-2466 3506 2466 3866 Dl
-2466 3866 1926 3866 Dl
-(user code) 1936 3708 w
-2196 3866 2196 4226 Dl
-2178 4154 2196 4226 Dl
-2214 4154 2196 4226 Dl
-1926 4586 1926 4226 Dl
-1926 4226 2466 4226 Dl
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-2466 4586 1926 4586 Dl
-(execac) 2014 4428 w
-2466 4406 2826 4406 Dl
-2754 4424 2826 4406 Dl
-2754 4388 2826 4406 Dl
-2826 4586 2826 4226 Dl
-2826 4226 3366 4226 Dl
-3366 4226 3366 4586 Dl
-3366 4586 2826 4586 Dl
-(runacore) 2860 4428 w
-8 /LucidaSansUnicode00 f
-(.) 3355 4409 w
-(.) 3391 4409 w
-(.) 3427 4409 w
-(.) 3463 4409 w
-(.) 3499 4409 w
-(.) 3535 4409 w
-(.) 3571 4409 w
-(.) 3607 4409 w
-(.) 3643 4409 w
-(.) 3679 4409 w
-(.) 3715 4409 w
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-3654 4388 3726 4406 Dl
-3726 4586 3726 4226 Dl
-3726 4226 4266 4226 Dl
-4266 4226 4266 4586 Dl
-4266 4586 3726 4586 Dl
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-(actouser) 3768 4428 w
-3996 4226 3996 3866 Dl
-4014 3938 3996 3866 Dl
-3978 3938 3996 3866 Dl
-3726 3866 3726 3506 Dl
-3726 3506 4266 3506 Dl
-4266 3506 4266 3866 Dl
-4266 3866 3726 3866 Dl
-(user code) 3736 3708 w
-(A) 720 4836 w
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-(new) 2122 4836 w
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 11 /LucidaSans-Italic f
-(execac) 3107 4836 w
-11 /LucidaSansUnicode00 f
-(\(or) 3519 4836 w
-(uses) 3727 4836 w
-(the) 4029 4836 w
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 11 /LucidaSans-Italic f
-(RFCORE) 4260 4836 w
-11 /LucidaSansUnicode00 f
-(flag) 4739 4836 w
-(in) 5001 4836 w
+(runac) 2720 5867 w
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 11 /LucidaSans-Italic f
-(rfork) 5161 4836 w
-11 /LucidaSansUnicode00 f
-(\)) 5436 4836 w
-(makes) 720 4966 w
-(the) 1112 4966 w
-(kernel) 1330 4966 w
-(call) 1710 4966 w
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 11 /LucidaSans-Italic f
-(runacore) 1938 4966 w
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-(in) 2470 4966 w
-(the) 2617 4966 w
-(context) 2835 4966 w
-(of) 3284 4966 w
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-(which) 3432 5096 w
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-(from) 4778 5096 w
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-(on) 5337 5096 w
-(on) 720 5226 w
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-(AC.) 1106 5226 w
-(To) 1368 5226 w
-(do) 1544 5226 w
-(so,) 1720 5226 w
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 11 /LucidaSans-Italic f
-(runacore) 1918 5226 w
-11 /LucidaSansUnicode00 f
-(calls) 2443 5226 w
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 11 /LucidaSans-Italic f
-(runac) 2720 5226 w
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-(to) 3070 5226 w
-(execute) 3217 5226 w
-11 /LucidaSans-Italic f
-(actouser) 3674 5226 w
-11 /LucidaSansUnicode00 f
-(on) 4173 5226 w
-(the) 4347 5226 w
-(AP) 4557 5226 w
-(selected.) 4733 5226 w
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-(control) 1231 5356 w
-(to) 1643 5356 w
-(user-mode,) 1787 5356 w
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-(state) 3181 5356 w
-(as) 3479 5356 w
-(saved) 3633 5356 w
-(in) 3975 5356 w
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-11 /LucidaSans-Italic f
-(Ureg) 4320 5356 w
-11 /LucidaSansUnicode00 f
-(kept) 4611 5356 w
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-11 /LucidaSansUnicode00 f
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-(to) 1759 5912 w
-(complete.) 1903 5912 w
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-(happens) 2740 5912 w
-(as) 3229 5912 w
-(soon) 3382 5912 w
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-(to) 4773 6208 w
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-(TC,) 5128 6208 w
-(by) 5346 6208 w
-(finishing) 720 6338 w
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-(and) 1713 6338 w
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-(spins) 4219 6338 w
-(on) 4545 6338 w
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-(struc\255) 5170 6338 w
-(ture) 720 6468 w
-(waiting for a) 971 6468 w
-(new) 1677 6468 w
-(call.) 1927 6468 w
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+(call.) 1927 7109 w
 cleartomark
 showpage
 saveobj restore
diff -r ddaa629716d5 -r 85df9273b945 src/9kron/k8/pmcio.c
--- a/src/9kron/k8/pmcio.c	Tue Jun 07 09:08:27 2011 +0000
+++ b/src/9kron/k8/pmcio.c	Tue Jun 07 11:18:59 2011 +0000
@@ -128,27 +128,24 @@
 
 	v = rdmsr(regno + PerfEvtbase);
 	v &= PeEvMskH|PeEvMskL|PeCtEna|PeOS|PeUsr|PeUnMsk;
-	if (p->enab != PmcCtlNullval){
+	if (p->enab != PmcCtlNullval)
 		if (p->enab)
 			v |= PeCtEna;
 		else
 			v &= ~PeCtEna;
-		p->enab = PmcCtlNullval;
-	}
-	if (p->user != PmcCtlNullval){
+
+	if (p->user != PmcCtlNullval)
 		if (p->user)
 			v |= PeUsr;
 		else
 			v &= ~PeUsr;
-		p->user = PmcCtlNullval;
-	}
-	if (p->os != PmcCtlNullval){
+
+	if (p->os != PmcCtlNullval)
 		if (p->os)
 			v |= PeOS;
 		else
 			v &= ~PeOS;
-		p->os = PmcCtlNullval;
-	}
+
 	if (pmctrans(p) < 0)
 		return -1;
 
@@ -161,12 +158,11 @@
 		v &= ~(PeEvMskL|PeEvMskH|PeUnMsk);
 		v |= SetEvMsk(v, e);
 		v |= SetUMsk(v, u);
-		p->nodesc = 1;
 	}
 	if (p->reset != PmcCtlNullval && p->reset) {
 		v = 0;
 		wrmsr(regno+ PerfCtrbase, 0);
-		p->reset = PmcCtlNullval;
+		p->reset = PmcCtlNullval; /* only reset once */
 	}
 	wrmsr(regno+ PerfEvtbase, v);
 	pmcuserenab(pmcanyenab());
diff -r ddaa629716d5 -r 85df9273b945 src/9kron2/include/libc.h
--- a/src/9kron2/include/libc.h	Tue Jun 07 09:08:27 2011 +0000
+++ b/src/9kron2/include/libc.h	Tue Jun 07 11:18:59 2011 +0000
@@ -743,7 +743,7 @@
 	PmcEnable = 4,
 };
 
-extern int confpmc(int, int, char *);
+extern int confpmc(int, int, int, char *);
 extern uvlong rdpmc(int);
 
 #pragma	varargck	argpos	werrstr	1
diff -r ddaa629716d5 -r 85df9273b945 src/9kron2/k8/pmcio.c
--- a/src/9kron2/k8/pmcio.c	Tue Jun 07 09:08:27 2011 +0000
+++ b/src/9kron2/k8/pmcio.c	Tue Jun 07 11:18:59 2011 +0000
@@ -128,27 +128,24 @@
 
 	v = rdmsr(regno + PerfEvtbase);
 	v &= PeEvMskH|PeEvMskL|PeCtEna|PeOS|PeUsr|PeUnMsk;
-	if (p->enab != PmcCtlNullval){
+	if (p->enab != PmcCtlNullval)
 		if (p->enab)
 			v |= PeCtEna;
 		else
 			v &= ~PeCtEna;
-		p->enab = PmcCtlNullval;
-	}
-	if (p->user != PmcCtlNullval){
+
+	if (p->user != PmcCtlNullval)
 		if (p->user)
 			v |= PeUsr;
 		else
 			v &= ~PeUsr;
-		p->user = PmcCtlNullval;
-	}
-	if (p->os != PmcCtlNullval){
+
+	if (p->os != PmcCtlNullval)
 		if (p->os)
 			v |= PeOS;
 		else
 			v &= ~PeOS;
-		p->os = PmcCtlNullval;
-	}
+
 	if (pmctrans(p) < 0)
 		return -1;
 
@@ -161,12 +158,11 @@
 		v &= ~(PeEvMskL|PeEvMskH|PeUnMsk);
 		v |= SetEvMsk(v, e);
 		v |= SetUMsk(v, u);
-		p->nodesc = 1;
 	}
 	if (p->reset != PmcCtlNullval && p->reset) {
 		v = 0;
 		wrmsr(regno+ PerfCtrbase, 0);
-		p->reset = PmcCtlNullval;
+		p->reset = PmcCtlNullval; /* only reset once */
 	}
 	wrmsr(regno+ PerfEvtbase, v);
 	pmcuserenab(pmcanyenab());
diff -r ddaa629716d5 -r 85df9273b945 src/9kron2/libc/port/confpmc.c
--- a/src/9kron2/libc/port/confpmc.c	Tue Jun 07 09:08:27 2011 +0000
+++ b/src/9kron2/libc/port/confpmc.c	Tue Jun 07 11:18:59 2011 +0000
@@ -2,12 +2,14 @@
 #include <libc.h>
 
 int
-confpmc(int index, int mode, char *desc)
+confpmc(int core, int index, int mode, char *desc)
 {
 	int fd;
 	char name[32];
 	
-	snprint(name, sizeof(name), "/dev/ctr%2.2udctl", index);
+	if(core < 0)
+		core = getcore(nil);
+	snprint(name, sizeof(name), "/dev/core%4.4d/ctr%2.2dctl", core, index);
 
 	fd = open(name, OWRITE);
 	if (fd < 0)
diff -r ddaa629716d5 -r 85df9273b945 src/9kron2/libc/port/rdpmc.c
--- a/src/9kron2/libc/port/rdpmc.c	Tue Jun 07 09:08:27 2011 +0000
+++ b/src/9kron2/libc/port/rdpmc.c	Tue Jun 07 11:18:59 2011 +0000
@@ -2,13 +2,16 @@
 #include <libc.h>
 
 
+
 uvlong
 rdpmc(int index)
 {
-	int fd, n;
+	int fd, n, core;
 	char name[16+2+1];	/* 0x0000000000000000\0 */
-	
-	snprint(name, sizeof(name), "/dev/ctr%2.2ud", index);
+
+	core = getcore(nil);
+
+	snprint(name, sizeof(name), "/dev/core%4.4d/ctr%2.2ud", core, index);
 
 	fd = open(name, OREAD);
 	if (fd < 0)
diff -r ddaa629716d5 -r 85df9273b945 src/9kron2/man/2/pmc
--- a/src/9kron2/man/2/pmc	Tue Jun 07 09:08:27 2011 +0000
+++ b/src/9kron2/man/2/pmc	Tue Jun 07 11:18:59 2011 +0000
@@ -7,7 +7,7 @@
 .B #include <libc.h>
 .PP
 .B
-int confpmc(int index, int mode, char *desc)
+int confpmc(int core, int index, int mode, char *desc)
 .PP
 .B
 uvlong rdpmc(int index)
@@ -15,6 +15,8 @@
 .I Confpmc
 configures the counter
 .I index
+on core
+.I core
 setting the configuration according to the configuration string,
 .I desc
 whic is architecture dependant and the
diff -r ddaa629716d5 -r 85df9273b945 src/9kron2/man/3/pmc
--- a/src/9kron2/man/3/pmc	Tue Jun 07 09:08:27 2011 +0000
+++ b/src/9kron2/man/3/pmc	Tue Jun 07 11:18:59 2011 +0000
@@ -5,20 +5,29 @@
 .nf
 .B bind '#ε' /dev
 
-.BI #ε/ctrdesc
-.BI #ε/ctr00
-.BI #ε/ctr00ctl
-.BI #ε/ctr01
-.BI #ε/ctr01ctl
+.BI #ε/core0000/ctrdesc
+.BI #ε/core0000/ctr00
+.BI #ε/core0000/ctr00ctl
+.BI #ε/core0000/ctr01
+.BI #ε/core0000/ctr01ctl
+ ...
+.BI #ε/core0001/ctr00
+.BI #ε/core0001/ctr00ctl
+.BI #ε/core0001/ctr01
+.BI #ε/core0001/ctr01ctl
  ...
 .fi
 .SH DESCRIPTION
 .PP
 The
 .I pmc
-device serves a one-level directory, giving
-access to the hardware counters on the processor
-the process reading or writing them is reading from.
+device serves a two-level directory, giving
+access to the hardware counters on the
+different cores.
+There is a directory per core,
+.B coreNNNN,
+containing files
+pertaining to that core.
 .PP
 The
 .B ctrNN
@@ -36,7 +45,7 @@
 .B os
 The counter only runs when the processor is in the kernel.
 .TP
-.BI set configuration
+.BI "set configuration
 Sets the counter configuration. The detail of what the configuration
 means is left to the specific implementation of the counter. Reading the
 .B ctrdesc
@@ -48,6 +57,11 @@
 any other way to access the counter from user space, like special
 instructions.
 .PP
+Any change to or from the counters or the configurations is seen
+as soon as possible. In the worst case, it is guaranteed that the values
+read or set are at least as fresh as the last time a process went in or out
+of the kernel on that core.
+.PP
 Configure the counter 0 to count L2 misses in the kernel.
 .EX
 	% bind '#ε' /dev
@@ -66,11 +80,11 @@
 		L2 ITLB miss
 		DRAM access
 		L3 miss
-	% echo reset > /dev/ctr00ctl
-	% echo kernel > /dev/ctr00ctl
-	% echo set L2 miss > /dev/ctr00ctl
-	% echo enable > /dev/ctr00ctl
-	% cat /dev/ctr00
+	% echo reset > /dev/core0000/ctr00ctl
+	% echo kernel > /dev/core0000/ctr00ctl
+	% echo set L2 miss > /dev/core0000/ctr00ctl
+	% echo enable > /dev/core0000/ctr00ctl
+	% cat /dev/core0000/ctr00
 		0x00000000000003e5
 	%
 .EE