it's not important to report on a "multiple irq botch" for isa irqs where
the second interrupt has the default settings.  this is almost certainly
because the default 1:1 mapping conflicted with an interrupt source
override from the APIC table.

Reference: /n/atom/patch/applied2013/squechisaoverride
Date: Tue Oct 22 07:59:30 CES 2013
Signed-off-by: quanstro@quanstro.net

--- /sys/src/nix/k10/ioapic.c	Tue Oct 22 07:57:31 2013
+++ /sys/src/nix/k10/ioapic.c	Tue Oct 22 07:57:32 2013
@@ -164,6 +164,11 @@
 		rdt->lo = lo;
 	}else{
 		if(lo != rdt->lo){
+			if(bustype == BusISA && intin < 16)
+			if(lo == (Im|IPhigh|TMedge)){
+				DBG("override: isa %d\n", intin);
+				return;	/* expected; default was overridden*/
+			}
 			print("mutiple irq botch type %d bus %d %d/%d/%d lo %.8ux vs %.8ux\n",
 				bustype, busno, apicno, intin, devno, lo, rdt->lo);
 			return;