pcireservemem is architecture dependent, so remove it from pci.c. this forces main.c to have a hook to initialize pci reserved memory. future work: just initialize pci at the beginning, and don't test for it later on. Reference: /n/atom/patch/applied2013/pcinoarchdep Date: Tue Sep 17 01:16:20 CES 2013 Signed-off-by: quanstro@quanstro.net --- /sys/src/nix/k10/pci.c Tue Sep 17 01:14:35 2013 +++ /sys/src/nix/k10/pci.c Tue Sep 17 01:14:35 2013 @@ -8,7 +8,7 @@ #include "io.h" #include "adr.h" -enum { +enum { /* configuration mechanism #1 */ PciADDR = 0xcf8, PciDATA = 0xcfc, @@ -96,39 +96,26 @@ } static int -fmtT(Fmt* fmt) +Tfmt(Fmt* fmt) { - char *p; - int l, r; - uint type, tbdf; - - if((p = malloc(READSTR)) == nil) - return fmtstrcpy(fmt, "(tbdfconv)"); - - switch(fmt->r){ - case 'T': - tbdf = va_arg(fmt->args, uint); - if(tbdf == -1){ - snprint(p, READSTR, "busunk"); - break; - } + char buf[32], *p, *e; + int type, tbdf; + + p = buf; + e = buf+sizeof buf; + tbdf = va_arg(fmt->args, int); + if(tbdf == -1) + return fmtstrcpy(fmt, "isa"); + if(fmt->flags & FmtLong){ type = BUSTYPE(tbdf); - if(type < nelem(bustypes)) - l = snprint(p, READSTR, bustypes[type]); + if(type == 12) + p = seprint(p, e, "pci."); else - l = snprint(p, READSTR, "%d", type); - snprint(p+l, READSTR-l, ".%d.%d.%d", - BUSBNO(tbdf), BUSDNO(tbdf), BUSFNO(tbdf)); - break; - - default: - snprint(p, READSTR, "(tbdfconv)"); - break; + p = seprint(p, e, "%d.", type); } - r = fmtstrcpy(fmt, p); - free(p); - - return r; + seprint(p, e, "%d.%d.%d", + BUSBNO(tbdf), BUSDNO(tbdf), BUSFNO(tbdf)); + return fmtstrcpy(fmt, buf); } static u32int @@ -266,12 +253,9 @@ } else { /* - * You can't go back. - * This shouldn't be possible, but the - * Iwill DK8-HTX seems to have subordinate - * bus numbers which get smaller on the - * way down. Need to look more closely at - * this. + * You can't go back. This shouldn't be possible, but the + * Iwill DK8-HTX seems to have decreasing subordinate + * bus numbers Need to look more closely at his. */ if(ubn > maxubn) maxubn = ubn; @@ -362,7 +346,6 @@ uchar checksum; }; - static void pcirouting(void) { @@ -447,22 +430,10 @@ } static void -pcireservemem(void) -{ - int i; - Pcidev *p; - - for(p = nil; p = pcimatch(p, 0, 0); ) - for(i=0; imem); i++) - if(p->mem[i].bar && (p->mem[i].bar&1) == 0) - adrmapinit(p->mem[i].bar&~0x0F, p->mem[i].size, Apcibar, Mfree); -} - -static void pcicfginit(void) { - int sbno, bno, n; - Pcidev **list, *p; + int bno, n; + Pcidev **list; if(pcicfgmode != -1) return; @@ -472,7 +443,7 @@ return; } - fmtinstall('T', fmtT); + fmtinstall('T', Tfmt); /* * Try to determine if PCI Mode1 configuration implemented. @@ -495,28 +466,13 @@ list = &pciroot; for(bno = 0; bno <= Maxbus; bno++) { - sbno = bno; bno = pcilscan(bno, list); - while(*list) + while(*list != nil) list = &(*list)->link; - if(sbno != 0) - continue; - /* - * If we have found a PCI-to-Cardbus bridge, make sure - * it has no valid mappings anymore. - */ - for(p = pciroot; p != nil; p = p->link){ - if (p->ccrb == 6 && p->ccru == 7) { - /* reset the cardbus */ - pcicfgw16(p, PciBCR, 0x40 | pcicfgr16(p, PciBCR)); - delay(50); - } - } } - if(pciroot != nil && getconf("*nopcirouting") == nil) - pcirouting(); - pcireservemem(); + pcirouting(); +// pcireservemem(); unlock(&pcicfginitlock); if(getconf("*pcihinv")) @@ -631,42 +587,35 @@ return p; } -static void -pcilhinv(Pcidev* p) +void +pcihinv(Pcidev* p) { int i; Pcidev *t; + if(p == nil) { + p = pciroot; + print("tbdf: type vid did intl memory\n"); + } for(t = p; t != nil; t = t->link) { - print("%d %2d/%d %.2ux %.2ux %.2ux %.4ux %.4ux %3d ", - BUSBNO(t->tbdf), BUSDNO(t->tbdf), BUSFNO(t->tbdf), - t->ccrb, t->ccru, t->ccrp, t->vid, t->did, t->intl); + print("%T: %.2ux %.4ux/%.4ux %.2d", + t->tbdf, t->ccru, t->vid, t->did, t->intl); for(i = 0; i < nelem(p->mem); i++) { if(t->mem[i].size == 0) continue; - print("%d:%.8ux %d ", i, t->mem[i].bar, t->mem[i].size); + print("%d:%.8ux %d ", i, + t->mem[i].bar, t->mem[i].size); } - if(t->bridge) + if(t->bridge != nil) print("->%d", BUSBNO(t->bridge->tbdf)); print("\n"); } - for(; p != nil; p = p->link) + while(p != nil) { if(p->bridge != nil) - pcilhinv(p->bridge); -} - -void -pcihinv(Pcidev* p) -{ - pcicfginit(); - lock(&pcicfginitlock); - if(p == nil){ - p = pciroot; - print("bus dev type vid did intl memory\n"); + pcihinv(p->bridge); + p = p->link; } - pcilhinv(p); - unlock(&pcicfginitlock); } void --- /sys/src/nix/k10/main.c Tue Sep 17 01:14:35 2013 +++ /sys/src/nix/k10/main.c Tue Sep 17 01:14:35 2013 @@ -150,8 +150,6 @@ m->perf.period = 1; hz = archhz(); - if(hz == 0) - panic("no hz"); m->cpuhz = hz; m->cyclefreq = hz; m->cpumhz = hz/1000000ll; @@ -164,6 +162,7 @@ meminit(); archinit(); mallocinit(); + archpciinit(); /* * Acpiinit will cause the first malloc. If the system dies here it's probably due --- /sys/src/nix/k10/archk10.c Tue Sep 17 01:14:36 2013 +++ /sys/src/nix/k10/archk10.c Tue Sep 17 01:14:36 2013 @@ -3,6 +3,8 @@ #include "mem.h" #include "dat.h" #include "fns.h" +#include "adr.h" +#include "io.h" static void k10archinit(void) @@ -226,4 +228,22 @@ r = rdtsc(); for(t = r + m->cpumhz*1000ull*ms; r < t; r = rdtsc()) pause(); +} + +static void +pcireservemem(void) +{ + int i; + Pcidev *p; + + for(p = nil; p = pcimatch(p, 0, 0); ) + for(i=0; imem); i++) + if(p->mem[i].bar && (p->mem[i].bar&1) == 0) + adrmapinit(p->mem[i].bar&~0x0F, p->mem[i].size, Apcibar, Mfree); +} + +void +archpciinit(void) +{ + pcireservemem(); }