partially decode the pci dcr (control) register as required to debug a driver issue. Reference: /n/atom/patch/applied2013/pcidcr Date: Sat Dec 21 03:26:45 CET 2013 Signed-off-by: quanstro@quanstro.net --- /sys/src/cmd/pci/pci.c Sat Dec 21 03:26:17 2013 +++ /sys/src/cmd/pci/pci.c Sat Dec 21 03:26:18 2013 @@ -30,11 +30,38 @@ Bprint(&o, "%s: %d lanes gen %d\n", s, lanes, gen); } +enum { + Errcorren = 1<<0, + Errnfatalen = 1<<1, /* non fatal */ + Fatalen = 1<<2, + Unsupen = 1<<3, + Relaxen = 1<<4, + Exttagen = 1<<8, + Phantomen = 1<<9, + Auxpwren = 1<<10, + Nosnoopen = 1<<11, +}; + +struct { + int v; + char *s; +} dcrtab[] = { + Errcorren, "errcorren", + Errnfatalen, "errnfatalen", + Fatalen, "fatalen", + Unsupen, "unsupen", + Relaxen, "relaxen", + Exttagen, "exttagen", + Phantomen, "phantomen", + Auxpwren, "auxpwren", + Nosnoopen, "nosnoopen", +}; + void pciedump(Pcidev *p, int off) { char *s, *si; - uint cap, i, j; + uint dcr, cap, i, j; cap = pcicfgr16(p, off + PciePCP); i = cap>>4 & 0xf; @@ -45,6 +72,14 @@ if(i == 4 || i == 6) si = cap&1<<8? "; slot": "; integrated"; Bprint(&o, " pcie type: %s%s; msgs %d\n", s, si, cap>>9 & 0x3f); + + dcr = pcicfgr16(p, off + PcieDCR); + Bprint(&o, " device control: %.4ux; ", dcr); + for(i = 0; i < nelem(dcrtab); i++){ + if(dcr & dcrtab[i].v) + Bprint(&o, "%s ", dcrtab[i].s); + } + Bprint(&o, "\n"); cap = pcicfgr32(p, off + PcieCAP); i = cap & 7;