- to prevent accidents of the usual conversions kind, pcicfgr32 returns a uint.
- make sure the mask for the bar physical address is of type uintmem.
- bars should be type uintmem, as they are physical addresses.  (we still only
honor 32-bit bars on k10, because that's what bios does.)

Reference: /n/atom/patch/applied2013/nixpciuintmem
Date: Tue Sep 17 03:51:34 CES 2013
Signed-off-by: quanstro@quanstro.net

--- /sys/src/nix/k10/io.h	Tue Sep 17 03:46:13 2013
+++ /sys/src/nix/k10/io.h	Tue Sep 17 03:46:14 2013
@@ -172,26 +172,6 @@
 	PciBCR		= 0x3E,		/* bridge control register */
 };
 
-enum {					/* type 2 pre-defined header */
-	PciCBExCA	= 0x10,
-	PciCBSPSR	= 0x16,
-	PciCBPBN	= 0x18,		/* primary bus number */
-	PciCBSBN	= 0x19,		/* secondary bus number */
-	PciCBUBN	= 0x1A,		/* subordinate bus number */
-	PciCBSLTR	= 0x1B,		/* secondary latency timer */
-	PciCBMBR0	= 0x1C,
-	PciCBMLR0	= 0x20,
-	PciCBMBR1	= 0x24,
-	PciCBMLR1	= 0x28,
-	PciCBIBR0	= 0x2C,		/* I/O base */
-	PciCBILR0	= 0x30,		/* I/O limit */
-	PciCBIBR1	= 0x34,		/* I/O base */
-	PciCBILR1	= 0x38,		/* I/O limit */
-	PciCBSVID	= 0x40,		/* subsystem vendor ID */
-	PciCBSID	= 0x42,		/* subsystem ID */
-	PciCBLMBAR	= 0x44,		/* legacy mode base address */
-};
-
 /* capabilities */
 enum {
 	PciCapPMG	= 0x01,		/* power management */
@@ -225,7 +205,7 @@
 	uchar	intl;			/* interrupt line */
 
 	struct {
-		u32int	bar;		/* base address */
+		uintmem	bar;		/* base address */
 		int	size;
 	} mem[6];
 
@@ -254,7 +234,7 @@
 void	archpciinit(void);
 int	pcicap(Pcidev*, int);
 int	pcicfgr16(Pcidev*, int);
-int	pcicfgr32(Pcidev*, int);
+uint	pcicfgr32(Pcidev*, int);
 int	pcicfgr8(Pcidev*, int);
 void	pcicfgw16(Pcidev*, int, int);
 void	pcicfgw32(Pcidev*, int, int);
--- /sys/src/nix/k10/pci.c	Tue Sep 17 03:46:17 2013
+++ /sys/src/nix/k10/pci.c	Tue Sep 17 03:46:19 2013
@@ -195,7 +195,7 @@
 				if((hdt & 0x7F) != 0)
 					break;
 				for(i = 0; i < nelem(p->mem); i++) {
-					p->mem[i].bar = pcicfgr32(p, PciBAR0+4*i);
+					p->mem[i].bar = (u32int)pcicfgr32(p, PciBAR0+4*i);
 					p->mem[i].size = pcibarsize(p, PciBAR0+4*i);
 				}
 				break;
@@ -472,7 +472,6 @@
 	}
 
 	pcirouting();
-//	pcireservemem();
 	unlock(&pcicfginitlock);
 
 	if(getconf("*pcihinv"))
@@ -551,7 +550,7 @@
 	pcicfgrw(p->tbdf, rno, data, Write, 2);
 }
 
-int
+uint
 pcicfgr32(Pcidev *p, int rno)
 {
 	return pcicfgrw(p->tbdf, rno, 0, Read, 4);
@@ -604,7 +603,7 @@
 		for(i = 0; i < nelem(p->mem); i++) {
 			if(t->mem[i].size == 0)
 				continue;
-			print("%d:%.8ux %d ", i,
+			print("%d:%#P %d ", i,
 				t->mem[i].bar, t->mem[i].size);
 		}
 		if(t->bridge != nil)
--- /sys/src/nix/k10/archk10.c	Tue Sep 17 03:46:21 2013
+++ /sys/src/nix/k10/archk10.c	Tue Sep 17 03:46:22 2013
@@ -219,7 +219,7 @@
 	for(p = nil; p = pcimatch(p, 0, 0); )
 		for(i=0; i<nelem(p->mem); i++)
 			if(p->mem[i].bar && (p->mem[i].bar&1) == 0)
-				adrmapinit(p->mem[i].bar&~0x0F, p->mem[i].size, Apcibar, Mfree);
+				adrmapinit(p->mem[i].bar&~(uintmem)0xf, p->mem[i].size, Apcibar, Mfree);
 }
 
 void
--- /sys/src/nix/k10/ether57711.c	Tue Sep 17 03:46:25 2013
+++ /sys/src/nix/k10/ether57711.c	Tue Sep 17 03:46:27 2013
@@ -272,13 +272,13 @@
 			print("%s: %T: too many controllers\n", cttab[type].name, p->tbdf);
 			continue;
 		}
-		mempa = p->mem[0].bar&~0xf;
+		mempa = p->mem[0].bar&~(uintmem)0xf;
 		mem = vmap(mempa, p->mem[0].size);
 		if(mem == 0){
 			print("%s: %T: cant map bar 0/reg\n", cttab[type].name, p->tbdf);
 			continue;
 		}
-		dbpa = p->mem[2].bar&~0xf;
+		dbpa = p->mem[2].bar&~(uintmem)0xf;
 		db = vmap(dbpa, p->mem[2].size);
 		if(db == 0){
 			print("%s: %T: cant map bar 2/db\n", cttab[type].name, p->tbdf);
--- /sys/src/nix/k10/etherigbe.c	Tue Sep 17 03:46:34 2013
+++ /sys/src/nix/k10/etherigbe.c	Tue Sep 17 03:46:37 2013
@@ -1962,9 +1962,9 @@
 			break;
 		}
 
-		mem = vmap(p->mem[0].bar & ~0x0F, p->mem[0].size);
+		mem = vmap(p->mem[0].bar & ~(uintmem)0xf, p->mem[0].size);
 		if(mem == nil){
-			print("igbe: can't map %#.8ux\n", p->mem[0].bar);
+			print("igbe: can't map %#P\n", p->mem[0].bar);
 			continue;
 		}
 		cls = pcicfgr8(p, PciCLS);
@@ -1986,7 +1986,7 @@
 			vunmap(mem, p->mem[0].size);
 			continue;
 		}
-		ctlr->port = p->mem[0].bar & ~0x0F;
+		ctlr->port = p->mem[0].bar & ~(uintmem)0xf;
 		ctlr->pcidev = p;
 		ctlr->id = (p->did<<16)|p->vid;
 		ctlr->cls = cls*4;
--- /sys/src/nix/k10/ether82563.c	Tue Sep 17 03:46:44 2013
+++ /sys/src/nix/k10/ether82563.c	Tue Sep 17 03:46:46 2013
@@ -422,10 +422,6 @@
 	Npool		= 10,
 };
 
-/*
- * cavet emptor: 82577/78 have been entered speculatitively.
- * awating datasheet from intel.
- */
 enum {
 	i82563,
 	i82566,
@@ -463,30 +459,30 @@
 	int	type;
 	int	mtu;
 	int	phyno;
-	int	flag;
 	char	*name;
+	int	flag;
 };
 
 static Ctlrtype cttab[Nctlrtype] = {
-	i82563,		9014,	1,	Fpba,		"i82563",
-	i82566,		1514,	1,	Fload,		"i82566",
-	i82567,		9234,	1,	Fload,		"i82567",
-	i82567m,		1514,	1,	0,		"i82567m",
-	i82571,		9234,	1,	Fpba,		"i82571",
-	i82572,		9234,	1,	Fpba,		"i82572",
-	i82573,		8192,	1,	Fert,		"i82573",		/* terrible perf above 8k */
-	i82574,		9018,	1,	0,		"i82574",
-	i82575,		9728,	1,	F75|Fflashea,	"i82575",
-	i82576,		9728,	1,	F75,		"i82576",
-	i82577,		4096,	2,	Fload|Fert,	"i82577",
-	i82577m,		1514,	2,	Fload|Fert,	"i82577",
-	i82578,		4096,	1,	Fload|Fert,	"i82578",
-	i82578m,		1514,	1,	Fload|Fert,	"i82578",
-	i82579,		9018,	2,	Fload|Fert|F79phy,	"i82579",
-	i82580,		9728,	1,	F75|F79phy,	"i82580",
-	i82583,		1514,	1,	0,		"i82583",
-	i210,		9728,	1,	F75|F79phy,	"i210",
-	i350,		9728,	1,	F75|F79phy,	"i350",
+	i82563,		9014,	1,	"i82563",		Fpba,
+	i82566,		1514,	1,	"i82566",		Fload,
+	i82567,		9234,	1,	"i82567",		Fload,
+	i82567m,		1514,	1,	"i82567m",	0,
+	i82571,		9234,	1,	"i82571",		Fpba,
+	i82572,		9234,	1,	"i82572",		Fpba,
+	i82573,		8192,	1,	"i82573",		Fert,		/* terrible perf above 8k */
+	i82574,		9018,	1,	"i82574",		0,
+	i82575,		9728,	1,	"i82575",		F75|Fflashea,
+	i82576,		9728,	1,	"i82576",		F75,
+	i82577,		4096,	2,	"i82577",		Fload|Fert,
+	i82577m,		1514,	2,	"i82577",		Fload|Fert,
+	i82578,		4096,	2,	"i82578",		Fload|Fert,
+	i82578m,		1514,	2,	"i82578",		Fload|Fert,
+	i82579,		9018,	2,	"i82579",		Fload|Fert|F79phy,
+	i82580,		9728,	1,	"i82580",		F75|F79phy,
+	i82583,		1514,	1,	"i82583",		0,
+	i210,		9728,	1,	"i210",		F75|F79phy,
+	i350,		9728,	1,	"i350",		F75|F79phy,
 };
 
 typedef void (*Freefn)(Block*);
@@ -1269,6 +1265,10 @@
 		else
 			return 0;
 		return phywrite0(c, phyno, pr, p);
+	case i82576:
+	case i82577:
+	case i82578:
+		return phywrite0(c, phyno, Phy79page, p);		/* unverified */
 	case i82579:
 		return phywrite0(c, phyno, Phy79page, p<<5);
 	default:
@@ -1571,7 +1571,7 @@
 {
 	Ctlr *ctlr;
 	Ether *edev;
-	int icr, im;
+	u32int icr, im;
 
 	edev = arg;
 	ctlr = edev->ctlr;
@@ -1749,7 +1749,7 @@
 	u16int sum;
 	Flash f;
 
-	io = c->pcidev->mem[1].bar & ~0x0f;
+	io = c->pcidev->mem[1].bar & ~(uintmem)0xf;
 	f.reg = vmap(io, c->pcidev->mem[1].size);
 	if(f.reg == nil)
 		return -1;
@@ -2016,7 +2016,7 @@
 		c->type = type;
 		c->pcidev = p;
 		c->rbsz = cttab[type].mtu;
-		c->port = p->mem[0].bar & ~0x0F;
+		c->port = p->mem[0].bar & ~(uintmem)0xf;
 		*cc = c;
 		cc = &c->next;
 	}
--- /sys/src/nix/k10/etherbcm.c	Tue Sep 17 03:46:50 2013
+++ /sys/src/nix/k10/etherbcm.c	Tue Sep 17 03:46:52 2013
@@ -801,7 +801,7 @@
 		if(ctlr == nil)
 			continue;
 		ctlr->type = type;
-		ctlr->port = p->mem[0].bar & ~0x0F;
+		ctlr->port = p->mem[0].bar & ~(uintmem)0xf;
 		mem = vmap(ctlr->port, p->mem[0].size);
 		if(mem == nil) {
 			print("bcm: can't map %#p\n", (uvlong)ctlr->port);
--- /sys/src/nix/k10/audiohda.c	Tue Sep 17 03:46:57 2013
+++ /sys/src/nix/k10/audiohda.c	Tue Sep 17 03:47:01 2013
@@ -1699,7 +1699,7 @@
 	ctlr->no = adev->ctlrno;
 	ctlr->size = p->mem[0].size;
 	ctlr->q = qopen(256, 0, 0, 0);
-	ctlr->mem = vmap(p->mem[0].bar & ~0x0F, ctlr->size);
+	ctlr->mem = vmap(p->mem[0].bar & ~(uintmem)0xf, ctlr->size);
 	if(ctlr->mem == nil){
 		print("#A%d: hda: can't map %.8ux\n", ctlr->no, p->mem[0].bar);
 		return -1;
--- /sys/src/nix/k10/ether82598.c	Tue Sep 17 03:47:05 2013
+++ /sys/src/nix/k10/ether82598.c	Tue Sep 17 03:47:07 2013
@@ -1129,7 +1129,7 @@
 			print("%s: %T: too many controllers\n", name, p->tbdf);
 			return;
 		}
-		io = p->mem[0].bar&~0xf;
+		io = p->mem[0].bar&~(uintmem)0xf;
 		mem = vmap(io, p->mem[0].size);
 		if(mem == 0){
 			print("%s: %T: cant map bar\n", name, p->tbdf);
--- /sys/src/nix/k10/etheriwl.c	Tue Sep 17 03:47:13 2013
+++ /sys/src/nix/k10/etheriwl.c	Tue Sep 17 03:47:17 2013
@@ -1929,8 +1929,8 @@
 			print("etheriwl: unable to alloc Ctlr\n");
 			continue;
 		}
-		ctlr->port = pdev->mem[0].bar & ~0x0F;
-		mem = vmap(pdev->mem[0].bar & ~0x0F, pdev->mem[0].size);
+		ctlr->port = pdev->mem[0].bar & ~(uintmem)0xf;
+		mem = vmap(ctlr->port, pdev->mem[0].size);
 		if(mem == nil) {
 			print("etheriwl: %T: can't map bars\n", pdev->tbdf);
 			free(ctlr);
--- /sys/src/nix/k10/usbehcipc.c	Tue Sep 17 03:47:20 2013
+++ /sys/src/nix/k10/usbehcipc.c	Tue Sep 17 03:47:22 2013
@@ -194,7 +194,7 @@
 			print("usbehci: ignore %.4ux/%.4ux\n", p->vid, p->did);
 			continue;
 		}
-		io = p->mem[0].bar & ~0x0f;
+		io = p->mem[0].bar & ~(uintmem)0xf;
 		if(io == 0){
 			print("usbehci: %x %x: failed to map registers\n",
 				p->vid, p->did);
--- /sys/src/nix/k10/sdahci.c	Tue Sep 17 03:47:27 2013
+++ /sys/src/nix/k10/sdahci.c	Tue Sep 17 03:47:30 2013
@@ -1840,7 +1840,7 @@
 		memset(c, 0, sizeof *c);
 		memset(s, 0, sizeof *s);
 		c->type = cttab + type;
-		io = p->mem[Abar].bar & ~0xf;
+		io = p->mem[Abar].bar & ~(uintmem)0xf;
 		c->mmio = vmap(io, p->mem[Abar].size);
 		if(c->mmio == nil){
 			print("%s: %T: address %#P in use\n",
--- /sys/src/nix/k10/sdodin.c	Tue Sep 17 03:47:36 2013
+++ /sys/src/nix/k10/sdodin.c	Tue Sep 17 03:47:40 2013
@@ -2122,7 +2122,7 @@
 {
 	uintptr io;
 
-	io = p->mem[bar].bar & ~0xf;
+	io = p->mem[bar].bar & ~(uintmem)0xf;
 	return (uint*)vmap(io, p->mem[bar].size);
 }
 
--- /sys/src/nix/k10/screen.c	Tue Sep 17 03:47:42 2013
+++ /sys/src/nix/k10/screen.c	Tue Sep 17 03:47:44 2013
@@ -523,7 +523,7 @@
 			best = i;
 	}
 	if(best >= 0){
-		paddr = p->mem[best].bar & ~0x0F;
+		paddr = p->mem[best].bar & ~(uintmem)0xf;
 		size = p->mem[best].size;
 		vgalinearaddr(scr, paddr, size);
 		return;
--- /sys/src/nix/k10/vgavesa.c	Tue Sep 17 03:47:46 2013
+++ /sys/src/nix/k10/vgavesa.c	Tue Sep 17 03:47:49 2013
@@ -152,7 +152,7 @@
 		if(pci->ccrb != Pcibcdisp)
 			continue;
 		for(i=0; i<nelem(pci->mem); i++)
-			if(paddr == (pci->mem[i].bar&~0x0F)){
+			if(paddr == (pci->mem[i].bar&~(uintmem)0xf)){
 				if(pci->mem[i].size > size)
 					size = pci->mem[i].size;
 				goto havesize;
--- /sys/src/nix/k10/etherm10g.c	Tue Sep 17 03:47:53 2013
+++ /sys/src/nix/k10/etherm10g.c	Tue Sep 17 03:47:56 2013
@@ -825,7 +825,7 @@
 	if(c->ramsz > p->mem[0].size)
 		return -1;
 
-	raddr = p->mem[0].bar & ~0x0F;
+	raddr = p->mem[0].bar & ~(uintmem)0xf;
 	mem = vmappat(raddr, p->mem[0].size, PATWC);
 	if(mem == nil){
 		print("m10g: can't map %P\n", (uintmem)p->mem[0].bar);
--- /sys/src/nix/k10/sdvanir.c	Tue Sep 17 03:48:01 2013
+++ /sys/src/nix/k10/sdvanir.c	Tue Sep 17 03:48:04 2013
@@ -2122,7 +2122,7 @@
 {
 	uintptr io;
 
-	io = p->mem[bar].bar & ~0xf;
+	io = p->mem[bar].bar & ~(uintmem)0xf;
 	return (uint*)vmap(io, p->mem[bar].size);
 }