add fetch-and-swap for amd64, and partially implement for 386.

issues:
- what should the relationship to ll/sc be?
- need implementations for arm, mips, power, power64

Reference: /n/atom/patch/applied2013/fas
Date: Thu Sep 26 10:58:58 CES 2013
Signed-off-by: quanstro@quanstro.net

--- /sys/src/libc/amd64/atom.s	Thu Sep 26 10:57:07 2013
+++ /sys/src/libc/amd64/atom.s	Thu Sep 26 10:57:07 2013
@@ -56,3 +56,14 @@
 _cas64r0:
 	DECL	AX
 	RET
+
+TEXT fas64(SB), 1, $-4
+TEXT fasp(SB), 1, $-4
+	MOVQ	p+8(FP), AX
+	LOCK; XCHGQ	AX, (RARG)			/*  */
+	RET
+
+TEXT fas32(SB), 1, $-4
+	MOVL	p+8(FP), AX
+	LOCK; XCHGL	AX, (RARG)			/*  */
+	RET
--- /sys/src/libc/386/atom.s	Thu Sep 26 10:57:08 2013
+++ /sys/src/libc/386/atom.s	Thu Sep 26 10:57:08 2013
@@ -73,3 +73,14 @@
 	JNE	fail
 	MOVL	$1,AX
 	RET
+
+//TEXT fas64(SB), 1, $-4
+//	MOVL	p+4(FP), BX
+//	LOCK; XCHGQ	BX, (AX)			/*  */
+//	RET
+
+TEXT fas32(SB), 1, $-4
+TEXT fasp(SB), 1, $-4
+	MOVL	p+4(FP), BX
+	LOCK; XCHGL	BX, (AX)			/*  */
+	RET
--- /sys/man/2/atom	Thu Sep 26 10:57:09 2013
+++ /sys/man/2/atom	Thu Sep 26 10:57:10 2013
@@ -1,6 +1,6 @@
 .TH ATOM 2
 .SH NAME
-ainc, adec, cas, cas32, cas64, casp, casl, loadlink, storecond, _tas \- atomic RMW operations
+ainc, adec, cas, cas32, cas64, casp, casl, fas32, fas64, fasp, loadlink, storecond, _tas \- atomic RMW operations
 .SH SYNOPSIS
 .B #include <u.h>
 .br
@@ -28,7 +28,16 @@
 int casl(ulong *addr, ulong ov, ulong nv);
 .PP
 .B
-int _tas(ulong *addr);
+u32int fas32(u32int *addr, u32int nv);
+.PP
+.B
+u64int fas64(u64int *addr, u64int nv);
+.PP
+.B
+void* fasp(void **addr, void *nv);
+.PP
+.B
+int _tas(int *addr);
 .PP
 .B
 ulong loadlink(ulong*);
@@ -70,6 +79,21 @@
 .I Store-Conditional ).
 These instructions are, however, emulated by the Plan 9 kernel.
 All other architectures have 32-bit CAS.
+.PP
+.IR Fas32 ,
+.IR fas64 ,
+and
+.I fasp 
+implement
+.I Fetch-and-Swap
+on, respectively,
+.IR u32int ,
+.IR u64int ,
+and
+.I void*
+values.  The availability of these functions depends on the
+\s-2CPU\s0 architecture, and implementation.  Currently
+there is only a full AMD64 implementation.
 .PP
 .I _tas
 implements