add the ability to debug sse on 386; correct MMX register definition for amd64

Reference: /n/atom/patch/applied2013/dbgsse386
Date: Fri May 31 21:34:02 CES 2013
Signed-off-by: quanstro@quanstro.net

--- /sys/lib/acid/386	Fri May 31 21:30:54 2013
+++ /sys/lib/acid/386	Fri May 31 21:30:55 2013
@@ -59,7 +59,7 @@
 	gpr();
 }
 
-defn fpr()
+defn x87regs()
 {
 	print("F0\t",  *F0, "\n");
 	print("F1\t",  *F1, "\n");
@@ -79,12 +79,54 @@
 	print("operand selector\t", *fmt(E6, 'x'), "\n");
 }
 
-defn mmregs()
+defn mregs()
+{
+	print("M0\t", *M0, " M1\t", *M1, "\n");
+	print("M2\t", *M2, " M3\t", *M3, "\n");
+	print("M4\t", *M4, " M5\t", *M5, "\n");
+	print("M6\t", *M6, " M7\t", *M7, "\n");
+}
+
+defn xregs()
+{
+	print("X0\t", *X0, " X1\t", *X1, "\n");
+	print("X2\t", *X2, " X3\t", *X3, "\n");
+	print("X4\t", *X4, " X5\t", *X5, "\n");
+	print("X6\t", *X6, " X7\t", *X7, "\n");
+}
+defn sseregs()
+{
+	print("FCW\t",	*FCW, " FSW\t",	*FSW, " FTW\t",	*FTW, "\n");
+	print("FOP\t",	*FOP, " FIP\t",	*FIP, " FCS\t",	*FCS, "\n");
+	print("FDP\t",	*FDP, " FDS\t",	*FDS, "\n");
+	print("MXCSR\t",	*MXCSR, " MXCSRMASK\t",	*MXCSRMASK, "\n");
+
+	mregs();
+	xregs();
+}
+
+fptype = "";
+defn fptype()
+{
+	local lines;
+
+	if fptype == "" then {
+		fptype = "x87";
+		lines = file("/dev/archctl");
+		if match("fp sse", lines) >= 0 then {
+			fptype = "pae";
+		}
+	}
+}
+
+defn fpr()
 {
-	print("MM0\t", *MM0, " MM1\t", *MM1, "\n");
-	print("MM2\t", *MM2, " MM3\t", *MM3, "\n");
-	print("MM4\t", *MM4, " MM5\t", *MM5, "\n");
-	print("MM6\t", *MM6, " MM7\t", *MM7, "\n");
+	fptype();
+	if fptype == "x87" then {
+		x87regs();
+	}else{
+		sseregs();
+	}
 }
 
 defn pstop(pid)
Binary files acid.orig and acid differ
Binary files db.orig and db differ
Binary files libmach.a.orig and libmach.a differ
--- /sys/src/libmach/6.c	Fri May 31 21:32:43 2013
+++ /sys/src/libmach/6.c	Fri May 31 21:32:44 2013
@@ -55,14 +55,14 @@
 	{"RDP",		FP_CTL(4),	RFLT, 'Y'},
 	{"MXCSR",	FP_CTL(6),	RFLT, 'X'},
 	{"MXCSRMASK",	FP_CTL(7),	RFLT, 'X'},
-	{"M0",		FP_REG(0),	RFLT, 'F'},	/* assumes double */
-	{"M1",		FP_REG(1),	RFLT, 'F'},
-	{"M2",		FP_REG(2),	RFLT, 'F'},
-	{"M3",		FP_REG(3),	RFLT, 'F'},
-	{"M4",		FP_REG(4),	RFLT, 'F'},
-	{"M5",		FP_REG(5),	RFLT, 'F'},
-	{"M6",		FP_REG(6),	RFLT, 'F'},
-	{"M7",		FP_REG(7),	RFLT, 'F'},
+	{"M0",		FP_REG(0),	RFLT, '3'},	/* assumes le 80 bit ieee */
+	{"M1",		FP_REG(1),	RFLT, '3'},
+	{"M2",		FP_REG(2),	RFLT, '3'},
+	{"M3",		FP_REG(3),	RFLT, '3'},
+	{"M4",		FP_REG(4),	RFLT, '3'},
+	{"M5",		FP_REG(5),	RFLT, '3'},
+	{"M6",		FP_REG(6),	RFLT, '3'},
+	{"M7",		FP_REG(7),	RFLT, '3'},
 	{"X0",		XM_REG(0),	RFLT, 'F'},	/* assumes double */
 	{"X1",		XM_REG(1),	RFLT, 'F'},
 	{"X2",		XM_REG(2),	RFLT, 'F'},
--- /sys/src/libmach/8.c	Fri May 31 21:32:45 2013
+++ /sys/src/libmach/8.c	Fri May 31 21:32:46 2013
@@ -14,8 +14,12 @@
 
 #define	REGSIZE		sizeof(struct Ureg)
 #define FP_CTL(x)	(REGSIZE+4*(x))
+#define FP_CTLS(x)	(REGSIZE+2*(x))
 #define FP_REG(x)	(FP_CTL(7)+10*(x))
-#define	FPREGSIZE	(7*4+8*10)
+#define M_REG(x)	(FP_CTL(8)+16*(x))
+#define X_REG(x)	(M_REG(8)+16*(x))
+//#define	FPREGSIZE	(7*4+8*10)
+#define	FPREGSIZE	(512)
 
 Reglist i386reglist[] = {
 	{"DI",		REGOFF(di),	RINT, 'X'},
@@ -52,6 +56,35 @@
 	{"F5",		FP_REG(5),	RFLT, '3'},
 	{"F6",		FP_REG(6),	RFLT, '3'},
 	{"F7",		FP_REG(7),	RFLT, '3'},
+
+	/* sse2 */
+	{"FCW",		FP_CTLS(0),	RFLT, 'x'},
+	{"FSW",		FP_CTLS(1),	RFLT, 'x'},
+	{"FTW",		FP_CTLS(2),	RFLT, 'b'},
+	{"FOP",		FP_CTLS(3),	RFLT, 'x'},
+	{"FIP",		FP_CTL(2),	RFLT, 'X'},	/**/
+	{"FCS",		FP_CTLS(6),	RFLT, 'x'},
+	{"FDP",		FP_CTL(4),	RFLT, 'X'},
+	{"FDS",		FP_CTLS(10),	RFLT, 'x'},
+	{"MXCSR",	FP_CTL(6),	RFLT, 'X'},
+	{"MXCSRMASK",	FP_CTL(7),	RFLT, 'X'},
+	{"M0",		M_REG(0),	RFLT, '3'},	/* assumes le 80 bit ieee */
+	{"M1",		M_REG(1),	RFLT, '3'},
+	{"M2",		M_REG(2),	RFLT, '3'},
+	{"M3",		M_REG(3),	RFLT, '3'},
+	{"M4",		M_REG(4),	RFLT, '3'},
+	{"M5",		M_REG(5),	RFLT, '3'},
+	{"M6",		M_REG(6),	RFLT, '3'},
+	{"M7",		M_REG(7),	RFLT, '3'},
+	{"X0",		X_REG(0),	RFLT, 'F'},	/* assumes double */
+	{"X1",		X_REG(1),	RFLT, 'F'},
+	{"X2",		X_REG(2),	RFLT, 'F'},
+	{"X3",		X_REG(3),	RFLT, 'F'},
+	{"X4",		X_REG(4),	RFLT, 'F'},
+	{"X5",		X_REG(5),	RFLT, 'F'},
+	{"X6",		X_REG(6),	RFLT, 'F'},
+	{"X7",		X_REG(7),	RFLT, 'F'},
+
 	{  0 }
 };
 
Binary files acid.1.orig and acid.1 differ
Binary files db.1.orig and db.1 differ