richard miller

the 5db change was previously applied

In armv6 and armv7, breakpoint instruction is conditionally executed, so use ALWAYS
condition in the instruction to ensure the breakpoint will be activated whatever the
condition code is in the PSR.  Unfortunately on kirkwood (and possibly other armv5?)
this changes the exception type from Undefined Instruction to Prefetch Abort, so trap.c
must be changed to allow for both possibilities.

After applying this patch, rebuild db and acid, and /arm/9plug if applicable.

Reference: /n/atom/patch/applied2013/arm-bkpt-cond
Date: Sun Aug  4 08:26:04 CES 2013
Signed-off-by: quanstro@quanstro.net

--- /sys/src/9/kw/trap.c	Sun Aug  4 08:25:37 2013
+++ /sys/src/9/kw/trap.c	Sun Aug  4 08:25:38 2013
@@ -417,6 +417,9 @@
 	case PsrMabt:			/* prefetch fault */
 		ldrexvalid = 0;
 		faultarm(ureg, ureg->pc, user, 1);
+		if(up->nnote == 0 &&
+		   (*(u32int*)ureg->pc & ~(0xF<<28)) == 0x01200070)
+			postnote(up, 1, "sys: breakpoint", NDebug);
 		break;
 	case PsrMabt+1:			/* data fault */
 		ldrexvalid = 0;
@@ -481,10 +484,9 @@
 	case PsrMund:	/* undefined instruction */
 		if(user){
 			if(seg(up, ureg->pc, 0) != nil &&
-			   *(u32int*)ureg->pc == 0xD1200070){
-				snprint(buf, sizeof buf, "sys: breakpoint");
-				postnote(up, 1, buf, NDebug);
-			}else{
+			   (*(u32int*)ureg->pc & ~(0xF<<28)) == 0x01200070)
+				postnote(up, 1, "sys: breakpoint", NDebug);
+			else{
 				/* look for floating point instructions to interpret */
 				x = spllo();
 				rv = fpiarm(ureg);