82567 actually uses phyno 2.

Reference: /n/atom/patch/applied2013/82576phyno
Date: Mon Jul 29 20:59:05 CES 2013
Signed-off-by: quanstro@quanstro.net

--- /sys/src/9/pc/ether82563.c	Mon Jul 29 20:58:49 2013
+++ /sys/src/9/pc/ether82563.c	Mon Jul 29 20:58:49 2013
@@ -178,6 +178,8 @@
 	Phypage		= 22,		/* 8256[34] page register */
 	Phystat		= 26,		/* 82580 phy status */
 	Phyapage	= 29,
+	Phy79page	= 31,		/* 82579 phy page register (all pages) */
+
 	Rtlink		= 1<<10,	/* realtime link status */
 	Phyan		= 1<<11,	/* phy has autonegotiated */
 
@@ -460,30 +462,31 @@
 struct Ctlrtype {
 	int	type;
 	int	mtu;
+	int	phyno;
 	int	flag;
 	char	*name;
 };
 
 static Ctlrtype cttab[Nctlrtype] = {
-	i82563,		9014,	Fpba,		"i82563",
-	i82566,		1514,	Fload,		"i82566",
-	i82567,		9234,	Fload,		"i82567",
-	i82567m,		1514,	0,		"i82567m",
-	i82571,		9234,	Fpba,		"i82571",
-	i82572,		9234,	Fpba,		"i82572",
-	i82573,		8192,	Fert,		"i82573",		/* terrible perf above 8k */
-	i82574,		9018,	0,		"i82574",
-	i82575,		9728,	F75|Fflashea,	"i82575",
-	i82576,		9728,	F75,		"i82576",
-	i82577,		4096,	Fload|Fert,	"i82577",
-	i82577m,		1514,	Fload|Fert,	"i82577",
-	i82578,		4096,	Fload|Fert,	"i82578",
-	i82578m,		1514,	Fload|Fert,	"i82578",
-	i82579,		9018,	Fload|Fert|F79phy,	"i82579",
-	i82580,		9728,	F75|F79phy,	"i82580",
-	i82583,		1514,	0,		"i82583",
-	i210,		9728,	F75|F79phy,	"i210",
-	i350,		9728,	F75|F79phy,	"i350",
+	i82563,		9014,	1,	Fpba,		"i82563",
+	i82566,		1514,	1,	Fload,		"i82566",
+	i82567,		9234,	1,	Fload,		"i82567",
+	i82567m,		1514,	1,	0,		"i82567m",
+	i82571,		9234,	1,	Fpba,		"i82571",
+	i82572,		9234,	1,	Fpba,		"i82572",
+	i82573,		8192,	1,	Fert,		"i82573",		/* terrible perf above 8k */
+	i82574,		9018,	1,	0,		"i82574",
+	i82575,		9728,	1,	F75|Fflashea,	"i82575",
+	i82576,		9728,	2,	F75,		"i82576",
+	i82577,		4096,	2,	Fload|Fert,	"i82577",
+	i82577m,		1514,	2,	Fload|Fert,	"i82577",
+	i82578,		4096,	1,	Fload|Fert,	"i82578",
+	i82578m,		1514,	1,	Fload|Fert,	"i82578",
+	i82579,		9018,	2,	Fload|Fert|F79phy,	"i82579",
+	i82580,		9728,	1,	F75|F79phy,	"i82580",
+	i82583,		1514,	1,	0,		"i82583",
+	i210,		9728,	1,	F75|F79phy,	"i210",
+	i350,		9728,	1,	F75|F79phy,	"i350",
 };
 
 typedef void (*Freefn)(Block*);
@@ -563,7 +566,7 @@
 			uint	starve;
 			Rendez;
 		};
-		uchar pad[128];		/* cacheline */
+		uchar pad[64];		/* cacheline */
 	};
 
 	Block	*x;
@@ -574,8 +577,7 @@
 #define csr32r(c, r)	(*((c)->nic+((r)/4)))
 #define csr32w(c, r, v)	(*((c)->nic+((r)/4)) = (v))
 
-static	Ctlr	*i82563ctlrhead;
-static	Ctlr	*i82563ctlrtail;
+static	Ctlr	*i82563ctlr;
 static	Rbpool	rbtab[Npool];
 
 static char *statistics[Nstatistics] = {
@@ -1251,8 +1253,33 @@
 	10, 100, 1000, 0
 };
 
+static uint phywrite0(Ctlr*, int, int, ushort);
+
 static uint
-phyread(Ctlr *c, int phyno, int reg)
+setpage(Ctlr *c, uint phyno, uint p, uint r)
+{
+	uint pr;
+
+	switch(c->type){
+	case i82563:
+		if(r >= 16 && r <= 28 && r != 22)
+			pr = Phypage;
+		else if(r == 30 || r == 31)
+			pr = Phyapage;
+		else
+			return 0;
+		return phywrite0(c, phyno, pr, p);
+	case i82579:
+		return phywrite0(c, phyno, Phy79page, p<<5);
+	default:
+		if(p == 0)
+			return 0;
+		return ~0;
+	}
+}
+
+static uint
+phyread0(Ctlr *c, int phyno, int reg)
 {
 	uint phy, i;
 
@@ -1272,6 +1299,16 @@
 }
 
 static uint
+phyread(Ctlr *c, uint phyno, uint reg)
+{
+	if(setpage(c, phyno, reg>>8, reg & 0xff) == ~0){
+		print("%s: phyread: bad phy page %d\n", cname(c), reg>>8);
+		return ~0;
+	}
+	return phyread0(c, phyno, reg & 0xff);
+}
+
+static uint
 phywrite0(Ctlr *c, int phyno, int reg, ushort val)
 {
 	uint phy, i;
@@ -1290,24 +1327,6 @@
 }
 
 static uint
-setpage(Ctlr *c, uint phyno, uint p, uint r)
-{
-	uint pr;
-
-	if(c->type == i82563){
-		if(r >= 16 && r <= 28 && r != 22)
-			pr = Phypage;
-		else if(r == 30 || r == 31)
-			pr = Phyapage;
-		else
-			return 0;
-		return phywrite0(c, phyno, pr, p);
-	}else if(p == 0)
-		return 0;
-	return ~0;
-}
-
-static uint
 phywrite(Ctlr *c, uint phyno, uint reg, ushort v)
 {
 	if(setpage(c, phyno, reg>>8, reg & 0xff) == ~0)
@@ -1316,12 +1335,12 @@
 }
 
 static void
-phyerrata(Ether *e, Ctlr *c)
+phyerrata(Ether *e, Ctlr *c, uint phyno)
 {
 	if(e->mbps == 0)
 		if(c->phyerrata == 0){
 			c->phyerrata++;
-			phywrite(c, 1, Phyprst, Prst);	/* try a port reset */
+			phywrite(c, phyno, Phyprst, Prst);	/* try a port reset */
 			print("%s: phy port reset\n", cname(c));
 		}
 	else
@@ -1338,10 +1357,7 @@
 	e = v;
 	c = e->ctlr;
 
-	phyno = 1;
-	if(c->type == i82579)
-		phyno = 2;
-
+	phyno = cttab[c->type].phyno;
 	for(;;){
 		phy = phyread(c, phyno, Phystat);
 		if(phy == ~0){
@@ -1371,17 +1387,18 @@
 static void
 phylproc(void *v)
 {
-	uint a, i, phy;
+	uint a, i, phy, phyno;
 	Ctlr *c;
 	Ether *e;
 
 	e = v;
 	c = e->ctlr;
+	phyno = cttab[c->type].phyno;
 
 	if(c->type == i82573 && (phy = phyread(c, 1, Phyier)) != ~0)
-		phywrite(c, 1, Phyier, phy | Lscie | Ancie | Spdie | Panie);
+		phywrite(c, phyno, Phyier, phy | Lscie | Ancie | Spdie | Panie);
 	for(;;){
-		phy = phyread(c, 1, Physsr);
+		phy = phyread(c, phyno, Physsr);
 		if(phy == ~0){
 			phy = 0;
 			i = 3;
@@ -1396,18 +1413,18 @@
 		case i82578:
 		case i82578m:
 		case i82583:
-			a = phyread(c, 1, Phyisr) & Ane;
+			a = phyread(c, phyno, Phyisr) & Ane;
 			break;
 		case i82571:
 		case i82572:
 		case i82575:
 		case i82576:
-			a = phyread(c, 1, Phylhr) & Anf;
+			a = phyread(c, phyno, Phylhr) & Anf;
 			i = (i-1) & 3;
 			break;
 		}
 		if(a)
-			phywrite(c, 1, Phyctl, phyread(c, 1, Phyctl) | Ran | Ean);
+			phywrite(c, phyno, Phyctl, phyread(c, phyno, Phyctl) | Ran | Ean);
 next:
 		e->link = (phy & Rtlink) != 0;
 		if(e->link == 0)
@@ -1415,7 +1432,7 @@
 		c->speeds[i]++;
 		e->mbps = speedtab[i];
 		if(c->type == i82563)
-			phyerrata(e, c);
+			phyerrata(e, c, phyno);
 		c->lim = 0;
 		i82563im(c, Lsc);
 		c->lsleep++;
@@ -1987,23 +2004,21 @@
 i82563pci(void)
 {
 	int type;
-	Ctlr *ctlr;
+	Ctlr *c, **cc;
 	Pcidev *p;
 
+	cc = &i82563ctlr;
 	for(p = nil; p = pcimatch(p, 0x8086, 0);){
 		hbafixup(p);
 		if((type = didtype(p->did)) == -1)
 			continue;
-		ctlr = malloc(sizeof(Ctlr));
-		ctlr->type = type;
-		ctlr->pcidev = p;
-		ctlr->rbsz = cttab[type].mtu;
-		ctlr->port = p->mem[0].bar & ~0x0F;
-		if(i82563ctlrhead != nil)
-			i82563ctlrtail->next = ctlr;
-		else
-			i82563ctlrhead = ctlr;
-		i82563ctlrtail = ctlr;
+		c = malloc(sizeof *c);
+		c->type = type;
+		c->pcidev = p;
+		c->rbsz = cttab[type].mtu;
+		c->port = p->mem[0].bar & ~0x0F;
+		*cc = c;
+		cc = &c->next;
 	}
 }
 
@@ -2045,7 +2060,7 @@
 	 * Any adapter matches if no edev->port is supplied,
 	 * otherwise the ports must match.
 	 */
-	for(ctlr = i82563ctlrhead; ; ctlr = ctlr->next){
+	for(ctlr = i82563ctlr; ; ctlr = ctlr->next){
 		if(ctlr == nil)
 			return -1;
 		if(ctlr->active)
--- /sys/src/9/pcpae/ether82563.c	Mon Jul 29 20:58:49 2013
+++ /sys/src/9/pcpae/ether82563.c	Mon Jul 29 20:58:49 2013
@@ -178,6 +178,8 @@
 	Phypage		= 22,		/* 8256[34] page register */
 	Phystat		= 26,		/* 82580 phy status */
 	Phyapage	= 29,
+	Phy79page	= 31,		/* 82579 phy page register (all pages) */
+
 	Rtlink		= 1<<10,	/* realtime link status */
 	Phyan		= 1<<11,	/* phy has autonegotiated */
 
@@ -460,30 +462,31 @@
 struct Ctlrtype {
 	int	type;
 	int	mtu;
+	int	phyno;
 	int	flag;
 	char	*name;
 };
 
 static Ctlrtype cttab[Nctlrtype] = {
-	i82563,		9014,	Fpba,		"i82563",
-	i82566,		1514,	Fload,		"i82566",
-	i82567,		9234,	Fload,		"i82567",
-	i82567m,		1514,	0,		"i82567m",
-	i82571,		9234,	Fpba,		"i82571",
-	i82572,		9234,	Fpba,		"i82572",
-	i82573,		8192,	Fert,		"i82573",		/* terrible perf above 8k */
-	i82574,		9018,	0,		"i82574",
-	i82575,		9728,	F75|Fflashea,	"i82575",
-	i82576,		9728,	F75,		"i82576",
-	i82577,		4096,	Fload|Fert,	"i82577",
-	i82577m,		1514,	Fload|Fert,	"i82577",
-	i82578,		4096,	Fload|Fert,	"i82578",
-	i82578m,		1514,	Fload|Fert,	"i82578",
-	i82579,		9018,	Fload|Fert|F79phy,	"i82579",
-	i82580,		9728,	F75|F79phy,	"i82580",
-	i82583,		1514,	0,		"i82583",
-	i210,		9728,	F75|F79phy,	"i210",
-	i350,		9728,	F75|F79phy,	"i350",
+	i82563,		9014,	1,	Fpba,		"i82563",
+	i82566,		1514,	1,	Fload,		"i82566",
+	i82567,		9234,	1,	Fload,		"i82567",
+	i82567m,		1514,	1,	0,		"i82567m",
+	i82571,		9234,	1,	Fpba,		"i82571",
+	i82572,		9234,	1,	Fpba,		"i82572",
+	i82573,		8192,	1,	Fert,		"i82573",		/* terrible perf above 8k */
+	i82574,		9018,	1,	0,		"i82574",
+	i82575,		9728,	1,	F75|Fflashea,	"i82575",
+	i82576,		9728,	2,	F75,		"i82576",
+	i82577,		4096,	2,	Fload|Fert,	"i82577",
+	i82577m,		1514,	2,	Fload|Fert,	"i82577",
+	i82578,		4096,	1,	Fload|Fert,	"i82578",
+	i82578m,		1514,	1,	Fload|Fert,	"i82578",
+	i82579,		9018,	2,	Fload|Fert|F79phy,	"i82579",
+	i82580,		9728,	1,	F75|F79phy,	"i82580",
+	i82583,		1514,	1,	0,		"i82583",
+	i210,		9728,	1,	F75|F79phy,	"i210",
+	i350,		9728,	1,	F75|F79phy,	"i350",
 };
 
 typedef void (*Freefn)(Block*);
@@ -563,7 +566,7 @@
 			uint	starve;
 			Rendez;
 		};
-		uchar pad[128];		/* cacheline */
+		uchar pad[64];		/* cacheline */
 	};
 
 	Block	*x;
@@ -574,8 +577,7 @@
 #define csr32r(c, r)	(*((c)->nic+((r)/4)))
 #define csr32w(c, r, v)	(*((c)->nic+((r)/4)) = (v))
 
-static	Ctlr	*i82563ctlrhead;
-static	Ctlr	*i82563ctlrtail;
+static	Ctlr	*i82563ctlr;
 static	Rbpool	rbtab[Npool];
 
 static char *statistics[Nstatistics] = {
@@ -1251,8 +1253,33 @@
 	10, 100, 1000, 0
 };
 
+static uint phywrite0(Ctlr*, int, int, ushort);
+
 static uint
-phyread(Ctlr *c, int phyno, int reg)
+setpage(Ctlr *c, uint phyno, uint p, uint r)
+{
+	uint pr;
+
+	switch(c->type){
+	case i82563:
+		if(r >= 16 && r <= 28 && r != 22)
+			pr = Phypage;
+		else if(r == 30 || r == 31)
+			pr = Phyapage;
+		else
+			return 0;
+		return phywrite0(c, phyno, pr, p);
+	case i82579:
+		return phywrite0(c, phyno, Phy79page, p<<5);
+	default:
+		if(p == 0)
+			return 0;
+		return ~0;
+	}
+}
+
+static uint
+phyread0(Ctlr *c, int phyno, int reg)
 {
 	uint phy, i;
 
@@ -1272,6 +1299,16 @@
 }
 
 static uint
+phyread(Ctlr *c, uint phyno, uint reg)
+{
+	if(setpage(c, phyno, reg>>8, reg & 0xff) == ~0){
+		print("%s: phyread: bad phy page %d\n", cname(c), reg>>8);
+		return ~0;
+	}
+	return phyread0(c, phyno, reg & 0xff);
+}
+
+static uint
 phywrite0(Ctlr *c, int phyno, int reg, ushort val)
 {
 	uint phy, i;
@@ -1290,24 +1327,6 @@
 }
 
 static uint
-setpage(Ctlr *c, uint phyno, uint p, uint r)
-{
-	uint pr;
-
-	if(c->type == i82563){
-		if(r >= 16 && r <= 28 && r != 22)
-			pr = Phypage;
-		else if(r == 30 || r == 31)
-			pr = Phyapage;
-		else
-			return 0;
-		return phywrite0(c, phyno, pr, p);
-	}else if(p == 0)
-		return 0;
-	return ~0;
-}
-
-static uint
 phywrite(Ctlr *c, uint phyno, uint reg, ushort v)
 {
 	if(setpage(c, phyno, reg>>8, reg & 0xff) == ~0)
@@ -1316,12 +1335,12 @@
 }
 
 static void
-phyerrata(Ether *e, Ctlr *c)
+phyerrata(Ether *e, Ctlr *c, uint phyno)
 {
 	if(e->mbps == 0)
 		if(c->phyerrata == 0){
 			c->phyerrata++;
-			phywrite(c, 1, Phyprst, Prst);	/* try a port reset */
+			phywrite(c, phyno, Phyprst, Prst);	/* try a port reset */
 			print("%s: phy port reset\n", cname(c));
 		}
 	else
@@ -1338,10 +1357,7 @@
 	e = v;
 	c = e->ctlr;
 
-	phyno = 1;
-	if(c->type == i82579)
-		phyno = 2;
-
+	phyno = cttab[c->type].phyno;
 	for(;;){
 		phy = phyread(c, phyno, Phystat);
 		if(phy == ~0){
@@ -1371,17 +1387,18 @@
 static void
 phylproc(void *v)
 {
-	uint a, i, phy;
+	uint a, i, phy, phyno;
 	Ctlr *c;
 	Ether *e;
 
 	e = v;
 	c = e->ctlr;
+	phyno = cttab[c->type].phyno;
 
 	if(c->type == i82573 && (phy = phyread(c, 1, Phyier)) != ~0)
-		phywrite(c, 1, Phyier, phy | Lscie | Ancie | Spdie | Panie);
+		phywrite(c, phyno, Phyier, phy | Lscie | Ancie | Spdie | Panie);
 	for(;;){
-		phy = phyread(c, 1, Physsr);
+		phy = phyread(c, phyno, Physsr);
 		if(phy == ~0){
 			phy = 0;
 			i = 3;
@@ -1396,18 +1413,18 @@
 		case i82578:
 		case i82578m:
 		case i82583:
-			a = phyread(c, 1, Phyisr) & Ane;
+			a = phyread(c, phyno, Phyisr) & Ane;
 			break;
 		case i82571:
 		case i82572:
 		case i82575:
 		case i82576:
-			a = phyread(c, 1, Phylhr) & Anf;
+			a = phyread(c, phyno, Phylhr) & Anf;
 			i = (i-1) & 3;
 			break;
 		}
 		if(a)
-			phywrite(c, 1, Phyctl, phyread(c, 1, Phyctl) | Ran | Ean);
+			phywrite(c, phyno, Phyctl, phyread(c, phyno, Phyctl) | Ran | Ean);
 next:
 		e->link = (phy & Rtlink) != 0;
 		if(e->link == 0)
@@ -1415,7 +1432,7 @@
 		c->speeds[i]++;
 		e->mbps = speedtab[i];
 		if(c->type == i82563)
-			phyerrata(e, c);
+			phyerrata(e, c, phyno);
 		c->lim = 0;
 		i82563im(c, Lsc);
 		c->lsleep++;
@@ -1987,23 +2004,21 @@
 i82563pci(void)
 {
 	int type;
-	Ctlr *ctlr;
+	Ctlr *c, **cc;
 	Pcidev *p;
 
+	cc = &i82563ctlr;
 	for(p = nil; p = pcimatch(p, 0x8086, 0);){
 		hbafixup(p);
 		if((type = didtype(p->did)) == -1)
 			continue;
-		ctlr = malloc(sizeof(Ctlr));
-		ctlr->type = type;
-		ctlr->pcidev = p;
-		ctlr->rbsz = cttab[type].mtu;
-		ctlr->port = p->mem[0].bar & ~0x0F;
-		if(i82563ctlrhead != nil)
-			i82563ctlrtail->next = ctlr;
-		else
-			i82563ctlrhead = ctlr;
-		i82563ctlrtail = ctlr;
+		c = malloc(sizeof *c);
+		c->type = type;
+		c->pcidev = p;
+		c->rbsz = cttab[type].mtu;
+		c->port = p->mem[0].bar & ~0x0F;
+		*cc = c;
+		cc = &c->next;
 	}
 }
 
@@ -2045,7 +2060,7 @@
 	 * Any adapter matches if no edev->port is supplied,
 	 * otherwise the ports must match.
 	 */
-	for(ctlr = i82563ctlrhead; ; ctlr = ctlr->next){
+	for(ctlr = i82563ctlr; ; ctlr = ctlr->next){
 		if(ctlr == nil)
 			return -1;
 		if(ctlr->active)
--- /sys/src/nix/k10/ether82563.c	Mon Jul 29 20:58:49 2013
+++ /sys/src/nix/k10/ether82563.c	Mon Jul 29 20:58:49 2013
@@ -178,6 +178,8 @@
 	Phypage		= 22,		/* 8256[34] page register */
 	Phystat		= 26,		/* 82580 phy status */
 	Phyapage	= 29,
+	Phy79page	= 31,		/* 82579 phy page register (all pages) */
+
 	Rtlink		= 1<<10,	/* realtime link status */
 	Phyan		= 1<<11,	/* phy has autonegotiated */
 
@@ -460,30 +462,31 @@
 struct Ctlrtype {
 	int	type;
 	int	mtu;
+	int	phyno;
 	int	flag;
 	char	*name;
 };
 
 static Ctlrtype cttab[Nctlrtype] = {
-	i82563,		9014,	Fpba,		"i82563",
-	i82566,		1514,	Fload,		"i82566",
-	i82567,		9234,	Fload,		"i82567",
-	i82567m,		1514,	0,		"i82567m",
-	i82571,		9234,	Fpba,		"i82571",
-	i82572,		9234,	Fpba,		"i82572",
-	i82573,		8192,	Fert,		"i82573",		/* terrible perf above 8k */
-	i82574,		9018,	0,		"i82574",
-	i82575,		9728,	F75|Fflashea,	"i82575",
-	i82576,		9728,	F75,		"i82576",
-	i82577,		4096,	Fload|Fert,	"i82577",
-	i82577m,		1514,	Fload|Fert,	"i82577",
-	i82578,		4096,	Fload|Fert,	"i82578",
-	i82578m,		1514,	Fload|Fert,	"i82578",
-	i82579,		9018,	Fload|Fert|F79phy,	"i82579",
-	i82580,		9728,	F75|F79phy,	"i82580",
-	i82583,		1514,	0,		"i82583",
-	i210,		9728,	F75|F79phy,	"i210",
-	i350,		9728,	F75|F79phy,	"i350",
+	i82563,		9014,	1,	Fpba,		"i82563",
+	i82566,		1514,	1,	Fload,		"i82566",
+	i82567,		9234,	1,	Fload,		"i82567",
+	i82567m,		1514,	1,	0,		"i82567m",
+	i82571,		9234,	1,	Fpba,		"i82571",
+	i82572,		9234,	1,	Fpba,		"i82572",
+	i82573,		8192,	1,	Fert,		"i82573",		/* terrible perf above 8k */
+	i82574,		9018,	1,	0,		"i82574",
+	i82575,		9728,	1,	F75|Fflashea,	"i82575",
+	i82576,		9728,	2,	F75,		"i82576",
+	i82577,		4096,	2,	Fload|Fert,	"i82577",
+	i82577m,		1514,	2,	Fload|Fert,	"i82577",
+	i82578,		4096,	1,	Fload|Fert,	"i82578",
+	i82578m,		1514,	1,	Fload|Fert,	"i82578",
+	i82579,		9018,	2,	Fload|Fert|F79phy,	"i82579",
+	i82580,		9728,	1,	F75|F79phy,	"i82580",
+	i82583,		1514,	1,	0,		"i82583",
+	i210,		9728,	1,	F75|F79phy,	"i210",
+	i350,		9728,	1,	F75|F79phy,	"i350",
 };
 
 typedef void (*Freefn)(Block*);
@@ -563,7 +566,7 @@
 			uint	starve;
 			Rendez;
 		};
-		uchar pad[128];		/* cacheline */
+		uchar pad[64];		/* cacheline */
 	};
 
 	Block	*x;
@@ -574,8 +577,7 @@
 #define csr32r(c, r)	(*((c)->nic+((r)/4)))
 #define csr32w(c, r, v)	(*((c)->nic+((r)/4)) = (v))
 
-static	Ctlr	*i82563ctlrhead;
-static	Ctlr	*i82563ctlrtail;
+static	Ctlr	*i82563ctlr;
 static	Rbpool	rbtab[Npool];
 
 static char *statistics[Nstatistics] = {
@@ -1251,8 +1253,33 @@
 	10, 100, 1000, 0
 };
 
+static uint phywrite0(Ctlr*, int, int, ushort);
+
 static uint
-phyread(Ctlr *c, int phyno, int reg)
+setpage(Ctlr *c, uint phyno, uint p, uint r)
+{
+	uint pr;
+
+	switch(c->type){
+	case i82563:
+		if(r >= 16 && r <= 28 && r != 22)
+			pr = Phypage;
+		else if(r == 30 || r == 31)
+			pr = Phyapage;
+		else
+			return 0;
+		return phywrite0(c, phyno, pr, p);
+	case i82579:
+		return phywrite0(c, phyno, Phy79page, p<<5);
+	default:
+		if(p == 0)
+			return 0;
+		return ~0;
+	}
+}
+
+static uint
+phyread0(Ctlr *c, int phyno, int reg)
 {
 	uint phy, i;
 
@@ -1272,6 +1299,16 @@
 }
 
 static uint
+phyread(Ctlr *c, uint phyno, uint reg)
+{
+	if(setpage(c, phyno, reg>>8, reg & 0xff) == ~0){
+		print("%s: phyread: bad phy page %d\n", cname(c), reg>>8);
+		return ~0;
+	}
+	return phyread0(c, phyno, reg & 0xff);
+}
+
+static uint
 phywrite0(Ctlr *c, int phyno, int reg, ushort val)
 {
 	uint phy, i;
@@ -1290,24 +1327,6 @@
 }
 
 static uint
-setpage(Ctlr *c, uint phyno, uint p, uint r)
-{
-	uint pr;
-
-	if(c->type == i82563){
-		if(r >= 16 && r <= 28 && r != 22)
-			pr = Phypage;
-		else if(r == 30 || r == 31)
-			pr = Phyapage;
-		else
-			return 0;
-		return phywrite0(c, phyno, pr, p);
-	}else if(p == 0)
-		return 0;
-	return ~0;
-}
-
-static uint
 phywrite(Ctlr *c, uint phyno, uint reg, ushort v)
 {
 	if(setpage(c, phyno, reg>>8, reg & 0xff) == ~0)
@@ -1316,12 +1335,12 @@
 }
 
 static void
-phyerrata(Ether *e, Ctlr *c)
+phyerrata(Ether *e, Ctlr *c, uint phyno)
 {
 	if(e->mbps == 0)
 		if(c->phyerrata == 0){
 			c->phyerrata++;
-			phywrite(c, 1, Phyprst, Prst);	/* try a port reset */
+			phywrite(c, phyno, Phyprst, Prst);	/* try a port reset */
 			print("%s: phy port reset\n", cname(c));
 		}
 	else
@@ -1338,10 +1357,7 @@
 	e = v;
 	c = e->ctlr;
 
-	phyno = 1;
-	if(c->type == i82579)
-		phyno = 2;
-
+	phyno = cttab[c->type].phyno;
 	for(;;){
 		phy = phyread(c, phyno, Phystat);
 		if(phy == ~0){
@@ -1371,17 +1387,18 @@
 static void
 phylproc(void *v)
 {
-	uint a, i, phy;
+	uint a, i, phy, phyno;
 	Ctlr *c;
 	Ether *e;
 
 	e = v;
 	c = e->ctlr;
+	phyno = cttab[c->type].phyno;
 
 	if(c->type == i82573 && (phy = phyread(c, 1, Phyier)) != ~0)
-		phywrite(c, 1, Phyier, phy | Lscie | Ancie | Spdie | Panie);
+		phywrite(c, phyno, Phyier, phy | Lscie | Ancie | Spdie | Panie);
 	for(;;){
-		phy = phyread(c, 1, Physsr);
+		phy = phyread(c, phyno, Physsr);
 		if(phy == ~0){
 			phy = 0;
 			i = 3;
@@ -1396,18 +1413,18 @@
 		case i82578:
 		case i82578m:
 		case i82583:
-			a = phyread(c, 1, Phyisr) & Ane;
+			a = phyread(c, phyno, Phyisr) & Ane;
 			break;
 		case i82571:
 		case i82572:
 		case i82575:
 		case i82576:
-			a = phyread(c, 1, Phylhr) & Anf;
+			a = phyread(c, phyno, Phylhr) & Anf;
 			i = (i-1) & 3;
 			break;
 		}
 		if(a)
-			phywrite(c, 1, Phyctl, phyread(c, 1, Phyctl) | Ran | Ean);
+			phywrite(c, phyno, Phyctl, phyread(c, phyno, Phyctl) | Ran | Ean);
 next:
 		e->link = (phy & Rtlink) != 0;
 		if(e->link == 0)
@@ -1415,7 +1432,7 @@
 		c->speeds[i]++;
 		e->mbps = speedtab[i];
 		if(c->type == i82563)
-			phyerrata(e, c);
+			phyerrata(e, c, phyno);
 		c->lim = 0;
 		i82563im(c, Lsc);
 		c->lsleep++;
@@ -1987,23 +2004,21 @@
 i82563pci(void)
 {
 	int type;
-	Ctlr *ctlr;
+	Ctlr *c, **cc;
 	Pcidev *p;
 
+	cc = &i82563ctlr;
 	for(p = nil; p = pcimatch(p, 0x8086, 0);){
 		hbafixup(p);
 		if((type = didtype(p->did)) == -1)
 			continue;
-		ctlr = malloc(sizeof(Ctlr));
-		ctlr->type = type;
-		ctlr->pcidev = p;
-		ctlr->rbsz = cttab[type].mtu;
-		ctlr->port = p->mem[0].bar & ~0x0F;
-		if(i82563ctlrhead != nil)
-			i82563ctlrtail->next = ctlr;
-		else
-			i82563ctlrhead = ctlr;
-		i82563ctlrtail = ctlr;
+		c = malloc(sizeof *c);
+		c->type = type;
+		c->pcidev = p;
+		c->rbsz = cttab[type].mtu;
+		c->port = p->mem[0].bar & ~0x0F;
+		*cc = c;
+		cc = &c->next;
 	}
 }
 
@@ -2045,7 +2060,7 @@
 	 * Any adapter matches if no edev->port is supplied,
 	 * otherwise the ports must match.
 	 */
-	for(ctlr = i82563ctlrhead; ; ctlr = ctlr->next){
+	for(ctlr = i82563ctlr; ; ctlr = ctlr->next){
 		if(ctlr == nil)
 			return -1;
 		if(ctlr->active)