keeping up with intel part numbers, rather than doing real work.

Reference: /n/atom/patch/applied/x552
Date: Mon Sep  7 21:58:37 CES 2015
Signed-off-by: quanstro@quanstro.net

--- /sys/src/9/pc/ether82598.c	Mon Sep  7 21:58:02 2015
+++ /sys/src/9/pc/ether82598.c	Mon Sep  7 21:58:03 2015
@@ -188,6 +188,7 @@
 	i82598,
 	i82599,
 	x540,
+	x550,
 	x552,
 	Nctlrtype,
 };
@@ -204,14 +205,16 @@
 	Fsplitivar	= 1<<1,	/* tx and rx use different ivar entries */
 	Fphyspd		= 1<<2,	/* phy speed useful (part supports <10gbe) */
 	Ftxctl		= 1<<3,	/* part has txctl register */
+	Feeskip45	= 1<<4,	/* eepom needs workds 4/5 skipped */
 };
 
 /* real mtu is 12k.  use standard 9k to save memory */
 static Ctlrtype cttab[Nctlrtype] = {
-	i82598,	9*1024,		Fsplitivar|Fphyoc,	"i82598",
-	i82599,	9*1024,		Fphyspd|Ftxctl,		"i82599",
-	x540,	9*1024,		Fphyspd|Ftxctl,		"x540",
-	x552,	9*1024,		Fphyspd|Ftxctl,		"x552",
+	i82598,	9*1024,		Fsplitivar|Fphyoc,		"i82598",
+	i82599,	9*1024,		Fphyspd|Ftxctl,			"i82599",
+	x540,	9*1024,		Fphyspd|Ftxctl|Feeskip45,		"x540",
+	x550,	9*1024,		Fphyspd|Ftxctl|Feeskip45,		"x550",
+	x552,	9*1024,		Fphyspd|Ftxctl|Feeskip45,		"x552",
 };
 
 struct Stat {
@@ -899,7 +902,7 @@
 	for(i = 0; i < 0x40; i++)
 		u +=  eeread(c, i);
 	for(i = 3; i < 0xf; i++){
-		if((c->type == x540 || c->type == x552) && (i == 4 || i == 5))
+		if((cttab[c->type].flag & Feeskip45) && (i == 4 || i == 5))
 			continue;
 		p = eeread(c, i);
 		l = eeread(c, p++);
@@ -1119,6 +1122,10 @@
 	case 0x1528:	/* x540-at2 “twinville” */
 	case 0x1560:
 		return x540;
+	case 0x1563:	/* x550-t */
+	case 0x15ae:	/* x550-em 1gbps */
+	case 0x15d1:	/* x550-t1 */
+		return x550;
 	case 0x15aa:	/* x552 backplane */
 	case 0x15ab:	/* x552 backplane */
 	case 0x15ac:	/* x552 sfp+ */
--- /sys/src/9/pcpae/ether82598.c	Mon Sep  7 21:58:06 2015
+++ /sys/src/9/pcpae/ether82598.c	Mon Sep  7 21:58:07 2015
@@ -188,6 +188,7 @@
 	i82598,
 	i82599,
 	x540,
+	x550,
 	x552,
 	Nctlrtype,
 };
@@ -204,14 +205,16 @@
 	Fsplitivar	= 1<<1,	/* tx and rx use different ivar entries */
 	Fphyspd		= 1<<2,	/* phy speed useful (part supports <10gbe) */
 	Ftxctl		= 1<<3,	/* part has txctl register */
+	Feeskip45	= 1<<4,	/* eepom needs workds 4/5 skipped */
 };
 
 /* real mtu is 12k.  use standard 9k to save memory */
 static Ctlrtype cttab[Nctlrtype] = {
-	i82598,	9*1024,		Fsplitivar|Fphyoc,	"i82598",
-	i82599,	9*1024,		Fphyspd|Ftxctl,		"i82599",
-	x540,	9*1024,		Fphyspd|Ftxctl,		"x540",
-	x552,	9*1024,		Fphyspd|Ftxctl,		"x552",
+	i82598,	9*1024,		Fsplitivar|Fphyoc,		"i82598",
+	i82599,	9*1024,		Fphyspd|Ftxctl,			"i82599",
+	x540,	9*1024,		Fphyspd|Ftxctl|Feeskip45,		"x540",
+	x550,	9*1024,		Fphyspd|Ftxctl|Feeskip45,		"x550",
+	x552,	9*1024,		Fphyspd|Ftxctl|Feeskip45,		"x552",
 };
 
 struct Stat {
@@ -899,7 +902,7 @@
 	for(i = 0; i < 0x40; i++)
 		u +=  eeread(c, i);
 	for(i = 3; i < 0xf; i++){
-		if((c->type == x540 || c->type == x552) && (i == 4 || i == 5))
+		if((cttab[c->type].flag & Feeskip45) && (i == 4 || i == 5))
 			continue;
 		p = eeread(c, i);
 		l = eeread(c, p++);
@@ -1119,6 +1122,10 @@
 	case 0x1528:	/* x540-at2 “twinville” */
 	case 0x1560:
 		return x540;
+	case 0x1563:	/* x550-t */
+	case 0x15ae:	/* x550-em 1gbps */
+	case 0x15d1:	/* x550-t1 */
+		return x550;
 	case 0x15aa:	/* x552 backplane */
 	case 0x15ab:	/* x552 backplane */
 	case 0x15ac:	/* x552 sfp+ */
--- /sys/src/nix/k10/ether82598.c	Mon Sep  7 21:58:10 2015
+++ /sys/src/nix/k10/ether82598.c	Mon Sep  7 21:58:11 2015
@@ -188,6 +188,7 @@
 	i82598,
 	i82599,
 	x540,
+	x550,
 	x552,
 	Nctlrtype,
 };
@@ -204,14 +205,16 @@
 	Fsplitivar	= 1<<1,	/* tx and rx use different ivar entries */
 	Fphyspd		= 1<<2,	/* phy speed useful (part supports <10gbe) */
 	Ftxctl		= 1<<3,	/* part has txctl register */
+	Feeskip45	= 1<<4,	/* eepom needs workds 4/5 skipped */
 };
 
 /* real mtu is 12k.  use standard 9k to save memory */
 static Ctlrtype cttab[Nctlrtype] = {
-	i82598,	9*1024,		Fsplitivar|Fphyoc,	"i82598",
-	i82599,	9*1024,		Fphyspd|Ftxctl,		"i82599",
-	x540,	9*1024,		Fphyspd|Ftxctl,		"x540",
-	x552,	9*1024,		Fphyspd|Ftxctl,		"x552",
+	i82598,	9*1024,		Fsplitivar|Fphyoc,		"i82598",
+	i82599,	9*1024,		Fphyspd|Ftxctl,			"i82599",
+	x540,	9*1024,		Fphyspd|Ftxctl|Feeskip45,		"x540",
+	x550,	9*1024,		Fphyspd|Ftxctl|Feeskip45,		"x550",
+	x552,	9*1024,		Fphyspd|Ftxctl|Feeskip45,		"x552",
 };
 
 struct Stat {
@@ -899,7 +902,7 @@
 	for(i = 0; i < 0x40; i++)
 		u +=  eeread(c, i);
 	for(i = 3; i < 0xf; i++){
-		if((c->type == x540 || c->type == x552) && (i == 4 || i == 5))
+		if((cttab[c->type].flag & Feeskip45) && (i == 4 || i == 5))
 			continue;
 		p = eeread(c, i);
 		l = eeread(c, p++);
@@ -1119,6 +1122,10 @@
 	case 0x1528:	/* x540-at2 “twinville” */
 	case 0x1560:
 		return x540;
+	case 0x1563:	/* x550-t */
+	case 0x15ae:	/* x550-em 1gbps */
+	case 0x15d1:	/* x550-t1 */
+		return x550;
 	case 0x15aa:	/* x552 backplane */
 	case 0x15ab:	/* x552 backplane */
 	case 0x15ac:	/* x552 sfp+ */