revert change -- second reboot doesn't work

Reference: /n/atom/patch/applied/pirebootrevert
Date: Sun Jan  3 20:57:01 CET 2016
Signed-off-by: quanstro@quanstro.net

--- /sys/src/9/bcm/rebootcode.s	Sun Jan  3 20:56:47 2016
+++ /sys/src/9/bcm/rebootcode.s	Sun Jan  3 20:56:48 2016
@@ -1,13 +1,8 @@
 /*
- * armv6/armv7 reboot code
+ * armv6 reboot code
  */
 #include "arm.s"
 
-#define PTEDRAM		(Dom0|L1AP(Krw)|Section)
-
-#define WFI	WORD	$0xe320f003	/* wait for interrupt */
-#define WFE	WORD	$0xe320f002	/* wait for event */
-
 /*
  * Turn off MMU, then copy the new kernel to its correct location
  * in physical memory.  Then jump to the start of the kernel.
@@ -20,7 +15,7 @@
 	/* copy in arguments before stack gets unmapped */
 	MOVW	R0, R8			/* entry point */
 	MOVW	p2+4(FP), R9		/* source */
-	MOVW	n+8(FP), R6		/* byte count */
+	MOVW	n+8(FP), R10		/* byte count */
 
 	/* SVC mode, interrupts disabled */
 	MOVW	$(PsrDirq|PsrDfiq|PsrMsvc), R1
@@ -34,28 +29,6 @@
 	BIC	$CpCmmu, R1
 	MCR	CpSC, 0, R1, C(CpCONTROL), C(0), CpMainctl
 
-	/* continue with reboot only on cpu0 */
-	CPUID(R2)
-	BEQ	bootcpu
-
-	/* other cpus wait for inter processor interrupt from cpu0 */
-	/* turn icache back on */
-	MRC	CpSC, 0, R1, C(CpCONTROL), C(0), CpMainctl
-	ORR	$(CpCicache), R1
-	MCR	CpSC, 0, R1, C(CpCONTROL), C(0), CpMainctl
-	BARRIERS
-dowfi:
-	WFI
-	MOVW	$0x40000060, R1
-	ADD		R2<<2, R1
-	MOVW	0(R1), R0
-	AND		$0x10, R0
-	BEQ		dowfi
-	MOVW	$0x8000, R1
-	BL		(R1)
-	B		dowfi
-
-bootcpu:
 	/* set up a tiny stack for local vars and memmove args */
 	MOVW	R8, SP			/* stack top just before kernel dest */
 	SUB	$20, SP			/* allocate stack frame */
@@ -64,12 +37,11 @@
 	MOVW	R8, 16(SP)		/* save dest (entry point) */
 	MOVW	R8, R0			/* first arg is dest */
 	MOVW	R9, 8(SP)		/* push src */
-	MOVW	R6, 12(SP)		/* push size */
+	MOVW	R10, 12(SP)		/* push size */
 	BL	memmove(SB)
 	MOVW	16(SP), R8		/* restore entry point */
 
 	/* jump to kernel physical entry point */
-	ORR	R8,R8
 	B	(R8)
 	B	0(PC)
 
@@ -79,38 +51,43 @@
  * clobbers R0-R2, and returns with SP invalid.
  */
 TEXT cachesoff(SB), 1, $-4
-	MOVM.DB.W [R14,R1-R10], (R13)		/* save regs on stack */
 
-	/* turn caches off, invalidate icache */
+	/* write back and invalidate caches */
+	BARRIERS
+	MOVW	$0, R0
+	MCR	CpSC, 0, R0, C(CpCACHE), C(CpCACHEwbi), CpCACHEall
+	MCR	CpSC, 0, R0, C(CpCACHE), C(CpCACHEinvi), CpCACHEall
+
+	/* turn caches off */
 	MRC	CpSC, 0, R1, C(CpCONTROL), C(0), CpMainctl
 	BIC	$(CpCdcache|CpCicache|CpCpredict), R1
 	MCR	CpSC, 0, R1, C(CpCONTROL), C(0), CpMainctl
-	MOVW	$0, R0
-	MCR	CpSC, 0, R0, C(CpCACHE), C(CpCACHEinvi), CpCACHEall
 
 	/* invalidate stale TLBs before changing them */
 	BARRIERS
-	MOVW	$0, R0
+	MOVW	$KZERO, R0			/* some valid virtual address */
 	MCR	CpSC, 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinv
 	BARRIERS
 
+	/* from here on, R0 is base of physical memory */
+	MOVW	$PHYSDRAM, R0
+
 	/* redo double map of first MiB PHYSDRAM = KZERO */
-	MOVW	12(R(MACH)), R2		/* m->mmul1 (virtual addr) */
+	MOVW	$(L1+L1X(PHYSDRAM)), R2		/* address of PHYSDRAM's PTE */
 	MOVW	$PTEDRAM, R1			/* PTE bits */
+	ORR	R0, R1				/* dram base */
 	MOVW	R1, (R2)
 
 	/* invalidate stale TLBs again */
 	BARRIERS
-	MOVW	$0, R0
 	MCR	CpSC, 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinv
 	BARRIERS
 
 	/* relocate SB and return address to PHYSDRAM addressing */
 	MOVW	$KSEGM, R1		/* clear segment bits */
 	BIC	R1, R12			/* adjust SB */
-	MOVM.IA.W (R13), [R14,R1-R10]		/* restore regs from stack */
-
-	MOVW	$KSEGM, R1		/* clear segment bits */
+	ORR	R0, R12
 	BIC	R1, R14			/* adjust return address */
+	ORR	R0, R14
 
 	RET
--- /sys/src/9/bcm/arm.s	Sun Jan  3 20:56:50 2016
+++ /sys/src/9/bcm/arm.s	Sun Jan  3 20:56:51 2016
@@ -11,6 +11,8 @@
 
 #define L1X(va)		(((((va))>>20) & 0x0fff)<<2)
 
+#define PTEDRAM		(Dom0|L1AP(Krw)|Section|Cached|Buffered)
+
 /*
  * new instructions
  */