add arg to mmuinit1 for multiprocessors

Reference: /n/atom/patch/applied/pimmuarg
Date: Sun Jan  3 19:46:12 CET 2016
Signed-off-by: quanstro@quanstro.net

--- /sys/src/9/bcm/mmu.c	Sun Jan  3 19:45:52 2016
+++ /sys/src/9/bcm/mmu.c	Sun Jan  3 19:45:53 2016
@@ -9,6 +9,9 @@
 #define FEXT(d, o, w)	(((d)>>(o)) & ((1<<(w))-1))
 #define L1X(va)		FEXT((va), 20, 12)
 #define L2X(va)		FEXT((va), 12, 8)
+#define L2AP(ap)	l2ap(ap)
+#define L1ptedramattrs	soc.l1ptedramattrs
+#define L2ptedramattrs	soc.l2ptedramattrs
 
 enum {
 	L1lo		= UZERO/MiB,		/* L1X(UZERO)? */
@@ -28,21 +31,21 @@
 	 * map all of ram at KZERO
 	 */
 	va = KZERO;
-	for(pa = PHYSDRAM; pa < PHYSDRAM+DRAMSIZE; pa += MiB){
-		l1[L1X(va)] = pa|Dom0|L1AP(Krw)|Section|Cached|Buffered;
+	for(pa = PHYSDRAM; pa < PHYSDRAM+soc.dramsize; pa += MiB){
+		l1[L1X(va)] = pa|Dom0|L1AP(Krw)|Section|L1ptedramattrs;
 		va += MiB;
 	}
 
 	/*
 	 * identity map first MB of ram so mmu can be enabled
 	 */
-	l1[L1X(PHYSDRAM)] = PHYSDRAM|Dom0|L1AP(Krw)|Section|Cached|Buffered;
+	l1[L1X(PHYSDRAM)] = PHYSDRAM|Dom0|L1AP(Krw)|Section|L1ptedramattrs;
 
 	/*
 	 * map i/o registers 
 	 */
 	va = VIRTIO;
-	for(pa = PHYSIO; pa < PHYSIO+IOSIZE; pa += MiB){
+	for(pa = soc.physio; pa < soc.physio+IOSIZE; pa += MiB){
 		l1[L1X(va)] = pa|Dom0|L1AP(Krw)|Section;
 		va += MiB;
 	}
@@ -52,15 +55,15 @@
 	 */
 	va = HVECTORS;
 	l1[L1X(va)] = (uintptr)l2|Dom0|Coarse;
-	l2[L2X(va)] = PHYSDRAM|L2AP(Krw)|Small;
+	l2[L2X(va)] = PHYSDRAM|L2AP(Krw)|Small|L2ptedramattrs;
 }
 
 void
-mmuinit1(void)
+mmuinit1(void *a)
 {
 	PTE *l1;
 
-	l1 = (PTE*)L1;
+	l1 = (PTE*)a;
 	m->mmul1 = l1;
 
 	/*
@@ -68,6 +71,10 @@
 	 */
 	l1[L1X(PHYSDRAM)] = 0;
 	cachedwbse(&l1[L1X(PHYSDRAM)], sizeof(PTE));
+	coherence();
+
+	cacheuwbinv();
+	l2cacheuwbinv();
 	mmuinvalidate();
 }
 
@@ -248,7 +255,7 @@
 	 */
 	x = Small;
 	if(!(pa & PTEUNCACHED))
-		x |= Cached|Buffered;
+		x |= L2ptedramattrs;
 	if(pa & PTEWRITE)
 		x |= L2AP(Urw);
 	else
@@ -266,14 +273,40 @@
 	 *  rather than direct mapped.
 	 */
 	cachedwbinv();
-	if(page->cachectl[0] == PG_TXTFLUSH){
+	if(page->cachectl[m->machno] == PG_TXTFLUSH){
 		/* pio() sets PG_TXTFLUSH whenever a text pg has been written */
 		cacheiinv();
-		page->cachectl[0] = PG_NOFLUSH;
+		page->cachectl[m->machno] = PG_NOFLUSH;
 	}
 	checkmmu(va, PPN(pa));
 }
 
+void*
+mmuuncache(void* v, usize size)
+{
+	int x;
+	PTE *pte;
+	uintptr va;
+
+	/*
+	 * Simple helper for ucalloc().
+	 * Uncache a Section, must already be
+	 * valid in the MMU.
+	 */
+	va = PTR2UINT(v);
+	assert(!(va & (1*MiB-1)) && size == 1*MiB);
+
+	x = L1X(va);
+	pte = &m->mmul1[x];
+	if((*pte & (Fine|Section|Coarse)) != Section)
+		return nil;
+	*pte &= ~(Cached|Buffered);
+	mmuinvalidateaddr(va);
+	cachedwbinvse(pte, 4);
+
+	return v;
+}
+
 /*
  * Return the number of bytes that can be accessed via KADDR(pa).
  * If pa is not a valid argument to KADDR, return 0.
@@ -306,7 +339,7 @@
 		*pte++ = (pa+n)|Dom0|L1AP(Krw)|Section;
 		mmuinvalidateaddr(va+n);
 	}
-	cachedwbse(pte0, (pte - pte0)*sizeof(PTE));
+	cachedwbse(pte0, (uintptr)pte - (uintptr)pte0);
 	return va + o;
 }
 
@@ -317,3 +350,4 @@
 	USED(va);
 	USED(pa);
 }
+
--- /sys/src/9/bcm/main.c	Sun Jan  3 19:45:55 2016
+++ /sys/src/9/bcm/main.c	Sun Jan  3 19:45:57 2016
@@ -255,7 +255,7 @@
 	m = (Mach*)MACHADDR;
 	memset(edata, 0, end - edata);	/* clear bss */
 	machinit();
-	mmuinit1();
+	mmuinit1((void*)L1);
 
 	optionsinit("/boot/boot boot");
 	fmtinit();
@@ -564,7 +564,6 @@
 {
 	void (*f)(ulong, ulong, ulong);
 
-	print("starting reboot...");
 	writeconf();
 	shutdown(0);
 
@@ -582,7 +581,10 @@
 	screenputs = nil;
 
 	/* shutdown devices */
-	chandevshutdown();
+	if(!waserror()){
+		chandevshutdown();
+		poperror();
+	}
 
 	/* stop the clock (and watchdog if any) */
 	clockshutdown();
--- /sys/src/9/bcm/fns.h	Sun Jan  3 19:45:59 2016
+++ /sys/src/9/bcm/fns.h	Sun Jan  3 19:46:00 2016
@@ -56,7 +56,7 @@
 extern void l2cachewbinv(void);
 extern void links(void);
 extern void mmuinit(void);
-extern void mmuinit1(void);
+extern void mmuinit1(void*);
 extern void mmuinvalidate(void);
 extern void mmuinvalidateaddr(u32int);
 extern uintptr mmukmap(uintptr, uintptr, usize);