remove macros for dma, and replace with functions. Reference: /n/atom/patch/applied/pidmanomacros Date: Sun Jan 3 07:34:09 CET 2016 Signed-off-by: quanstro@quanstro.net --- /sys/src/9/bcm/io.h Sun Jan 3 07:33:39 2016 +++ /sys/src/9/bcm/io.h Sun Jan 3 07:33:40 2016 @@ -43,5 +43,5 @@ ClkPixel, ClkPwm, - TempDefault = 0, /* Specification says "id should be 0" */ + TempCpu = 0, }; --- /sys/src/9/bcm/vcore.c Sun Jan 3 07:33:42 2016 +++ /sys/src/9/bcm/vcore.c Sun Jan 3 07:33:43 2016 @@ -33,6 +33,7 @@ TagResp = 1<<31, TagGetfwrev = 0x00000001, + TagGetrev = 0x00010002, TagGetmac = 0x00010003, TagGetram = 0x00010005, TagGetpower = 0x00020001, @@ -115,7 +116,8 @@ uintptr r; int n; Prophdr *prop; - static uintptr base = BUSDRAM; + uintptr aprop; + static int busaddr = 1; if(rsplen < vallen) rsplen = vallen; @@ -132,13 +134,14 @@ memmove(prop->data, buf, vallen); cachedwbinvse(prop, prop->len); for(;;){ - vcwrite(ChanProps, PADDR(prop) + base); + aprop = busaddr? dmaaddr(prop) : PTR2UINT(prop); + vcwrite(ChanProps, aprop); r = vcread(ChanProps); - if(r == PADDR(prop) + base) + if(r == aprop) break; - if(base == 0) + if(!busaddr) return -1; - base = 0; + busaddr = 0; } if(prop->req == RspOk && prop->tag == tag && @@ -186,7 +189,7 @@ fi->yres = fi->yresvirtual = *height; fi->bpp = *depth; cachedwbinvse(fi, sizeof(*fi)); - vcwrite(ChanFb, DMAADDR(fi)); + vcwrite(ChanFb, dmaaddr(fi)); if(vcread(ChanFb) != 0) return 0; va = mmukmap(FRAMEBUFFER, PADDR(fi->base), fi->screensize); @@ -252,6 +255,19 @@ } /* + * Get board revision + */ +uint +getboardrev(void) +{ + u32int buf[1]; + + if(vcreq(TagGetrev, buf, 0, sizeof buf) != sizeof buf) + return 0; + return buf[0]; +} + +/* * Get firmware revision */ uint @@ -299,6 +315,7 @@ gettemp(int tempid) { u32int buf[2]; + buf[0] = tempid; if(vcreq(TagGettemp, buf, sizeof(buf[0]), sizeof(buf)) != sizeof buf) return 0; --- /sys/src/9/bcm/main.c Sun Jan 3 07:33:46 2016 +++ /sys/src/9/bcm/main.c Sun Jan 3 07:33:47 2016 @@ -249,7 +249,7 @@ main(void) { extern char edata[], end[]; - uint rev; + uint fw, board; okay(1); m = (Mach*)MACHADDR; @@ -268,9 +268,10 @@ screeninit(); print("\nPlan 9 from Bell Labs\n"); - rev = getfirmware(); - print("firmware: rev %d\n", rev); - if(rev < Minfirmrev){ + board = getboardrev(); + fw = getfirmware(); + print("board rev: %#ux firmware rev: %d\n", board, fw); + if(fw < Minfirmrev){ print("Sorry, firmware (start*.elf) must be at least rev %d" " or newer than %s\n", Minfirmrev, Minfirmdate); for(;;) @@ -593,6 +594,7 @@ f = (void*)REBOOTADDR; memmove(f, rebootcode, sizeof(rebootcode)); cacheuwbinv(); + l2cacheuwbinv(); /* off we go - never to return */ (*f)(PADDR(entry), PADDR(code), size); --- /sys/src/9/bcm/dma.c Sun Jan 3 07:33:49 2016 +++ /sys/src/9/bcm/dma.c Sun Jan 3 07:33:50 2016 @@ -1,11 +1,3 @@ -#include "u.h" -#include "../port/lib.h" -#include "../port/error.h" -#include "mem.h" -#include "dat.h" -#include "fns.h" -#include "io.h" - /* * bcm2835 dma controller * @@ -18,60 +10,68 @@ * Experiments show that only channels 2-5,11-12 work with mmc */ +#include "u.h" +#include "../port/lib.h" +#include "../port/error.h" +#include "mem.h" +#include "dat.h" +#include "fns.h" +#include "io.h" + #define DMAREGS (VIRTIO+0x7000) #define DBG if(Dbg) enum { - Nchan = 7, /* number of dma channels */ - Regsize = 0x100, /* size of regs for each chan */ - Cbalign = 32, /* control block byte alignment */ - Dbg = 0, + Nchan = 7, /* number of dma channels */ + Regsize = 0x100, /* size of regs for each chan */ + Cbalign = 32, /* control block byte alignment */ + Dbg = 0, -/* registers for each dma controller */ - Cs = 0x00>>2, - Conblkad = 0x04>>2, - Ti = 0x08>>2, - Sourcead = 0x0c>>2, - Destad = 0x10>>2, - Txfrlen = 0x14>>2, - Stride = 0x18>>2, - Nextconbk = 0x1c>>2, - Debug = 0x20>>2, - -/* collective registers */ - Intstatus = 0xfe0>>2, - Enable = 0xff0>>2, - -/* Cs */ - Reset = 1<<31, - Abort = 1<<30, - Error = 1<<8, - Waitwrite = 1<<6, - Waitdreq = 1<<5, - Paused = 1<<4, - Dreq = 1<<3, - Int = 1<<2, - End = 1<<1, - Active = 1<<0, - -/* Ti */ - Permapshift = 16, - Srcignore = 1<<11, - Srcdreq = 1<<10, - Srcwidth128 = 1<<9, - Srcinc = 1<<8, - Destignore = 1<<7, - Destdreq = 1<<6, + /* registers for each dma controller */ + Cs = 0x00>>2, + Conblkad = 0x04>>2, + Ti = 0x08>>2, + Sourcead = 0x0c>>2, + Destad = 0x10>>2, + Txfrlen = 0x14>>2, + Stride = 0x18>>2, + Nextconbk = 0x1c>>2, + Debug = 0x20>>2, + + /* collective registers */ + Intstatus = 0xfe0>>2, + Enable = 0xff0>>2, + + /* Cs */ + Reset = 1<<31, + Abort = 1<<30, + Error = 1<<8, + Waitwrite = 1<<6, + Waitdreq = 1<<5, + Paused = 1<<4, + Dreq = 1<<3, + Int = 1<<2, + End = 1<<1, + Active = 1<<0, + + /* Ti */ + Permapshift= 16, + Srcignore = 1<<11, + Srcdreq = 1<<10, + Srcwidth128 = 1<<9, + Srcinc = 1<<8, + Destignore = 1<<7, + Destdreq = 1<<6, Destwidth128 = 1<<5, - Destinc = 1<<4, - Waitresp = 1<<3, - Tdmode = 1<<1, - Inten = 1<<0, - -/* Debug */ - Lite = 1<<28, - Clrerrors = 7<<0, + Destinc = 1<<4, + Waitresp = 1<<3, + Tdmode = 1<<1, + Inten = 1<<0, + + /* Debug */ + Lite = 1<<28, + Clrerrors = 7<<0, }; typedef struct Ctlr Ctlr; @@ -79,9 +79,9 @@ struct Ctlr { u32int *regs; - Cb *cb; + Cb *cb; Rendez r; - int dmadone; + int dmadone; }; struct Cb { @@ -97,6 +97,18 @@ static Ctlr dma[Nchan]; static u32int *dmaregs = (u32int*)DMAREGS; +uintptr +dmaaddr(void *va) +{ + return soc.busdram | (PTR2UINT(va) & ~KSEGM); +} + +static uintptr +dmaioaddr(void *va) +{ + return soc.busio | (PTR2UINT(va) & ~VIRTIO); +} + static void dump(char *msg, uchar *p, int n) { @@ -148,7 +160,7 @@ assert(ctlr->cb != nil); dmaregs[Enable] |= 1<regs[Cs] = Reset; - while(ctlr->regs[Cs]&Reset) + while(ctlr->regs[Cs] & Reset) ; intrenable(IRQDMA(chan), dmainterrupt, ctlr, 0, "dma"); } @@ -158,21 +170,21 @@ case DmaD2M: cachedwbinvse(dst, len); ti = Srcdreq | Destinc; - cb->sourcead = DMAIO(src); - cb->destad = DMAADDR(dst); + cb->sourcead = dmaioaddr(src); + cb->destad = dmaaddr(dst); break; case DmaM2D: cachedwbse(src, len); ti = Destdreq | Srcinc; - cb->sourcead = DMAADDR(src); - cb->destad = DMAIO(dst); + cb->sourcead = dmaaddr(src); + cb->destad = dmaioaddr(dst); break; case DmaM2M: cachedwbse(src, len); cachedwbinvse(dst, len); ti = Srcinc | Destinc; - cb->sourcead = DMAADDR(src); - cb->destad = DMAADDR(dst); + cb->sourcead = dmaaddr(src); + cb->destad = dmaaddr(dst); break; } cb->ti = ti | dev<regs[Cs] = 0; microdelay(1); - ctlr->regs[Conblkad] = DMAADDR(cb); + ctlr->regs[Conblkad] = dmaaddr(cb); DBG print("dma start: %ux %ux %ux %ux %ux %ux\n", - cb->ti, cb->sourcead, cb->destad, cb->txfrlen, cb->stride, cb->nextconbk); + cb->ti, cb->sourcead, cb->destad, cb->txfrlen, + cb->stride, cb->nextconbk); DBG print("intstatus %ux\n", dmaregs[Intstatus]); dmaregs[Intstatus] = 0; ctlr->regs[Cs] = Int; --- /sys/src/9/bcm/fns.h Sun Jan 3 07:33:52 2016 +++ /sys/src/9/bcm/fns.h Sun Jan 3 07:33:53 2016 @@ -19,12 +19,15 @@ extern void clockshutdown(void); extern int cmpswap(long*, long, long); extern void coherence(void); +extern u32int cpidget(void); extern ulong cprd(int cp, int op1, int crn, int crm, int op2); extern ulong cprdsc(int op1, int crn, int crm, int op2); extern void cpuidprint(void); +extern char *cputype2name(char *buf, int size); extern void cpwr(int cp, int op1, int crn, int crm, int op2, ulong val); extern void cpwrsc(int op1, int crn, int crm, int op2, ulong val); #define cycles(ip) *(ip) = lcycles() +extern uintptr dmaaddr(void *va); extern void dmastart(int, int, int, void*, void*, int); extern int dmawait(int); extern int fbblank(int); @@ -37,6 +40,7 @@ extern ulong fpsavereg(int fpreg, uvlong *fpp); extern void fpwr(int fpreg, ulong val); extern u32int fsrget(void); +extern uint getboardrev(void); extern ulong getclkrate(int); extern char* getconf(char*); extern char *getethermac(void); @@ -48,6 +52,7 @@ extern void irqenable(int, void (*)(Ureg*, void*), void*); #define intrenable(i, f, a, b, n) irqenable((i), (f), (a)) extern void intrsoff(void); +extern int l2ap(int); extern void links(void); extern void mmuinit(void); extern void mmuinit1(void); @@ -65,7 +70,6 @@ extern int splflo(void); extern void swcursorinit(void); extern void syscallfmt(int syscallno, ulong pc, va_list list); -extern void sysretfmt(int syscallno, va_list list, long ret, uvlong start, uvlong stop); extern int tas(void *); extern void touser(uintptr); extern void trapinit(void); @@ -113,7 +117,5 @@ #define KADDR(pa) UINT2PTR(KZERO | ((uintptr)(pa) & ~KSEGM)) #define PADDR(va) PTR2UINT(PHYSDRAM | ((uintptr)(va) & ~KSEGM)) -#define DMAADDR(va) PTR2UINT(BUSDRAM | ((uintptr)(va) & ~KSEGM)) -#define DMAIO(va) PTR2UINT(BUSIO | ((uintptr)(va) & ~VIRTIO)) #define MASK(v) ((1UL << (v)) - 1) /* mask `v' bits wide */