from richard: make v6 mmuinit compatible with v7

Reference: /n/atom/patch/applied/piarm6upd
Date: Sun Jan  3 20:09:24 CET 2016
Signed-off-by: quanstro@quanstro.net

--- /sys/src/9/bcm/mmu.c	Sun Jan  3 20:07:51 2016
+++ /sys/src/9/bcm/mmu.c	Sun Jan  3 20:07:53 2016
@@ -19,12 +19,12 @@
 };
 
 void
-mmuinit(void)
+mmuinit(void *a)
 {
 	PTE *l1, *l2;
 	uintptr pa, va;
 
-	l1 = (PTE*)PADDR(L1);
+	l1 = (PTE*)a;
 	l2 = (PTE*)PADDR(L2);
 
 	/*
@@ -49,6 +49,9 @@
 		l1[L1X(va)] = pa|Dom0|L1AP(Krw)|Section;
 		va += MiB;
 	}
+	pa = soc.armlocal;
+	if(pa)
+		l1[L1X(va)] = pa|Dom0|L1AP(Krw)|Section;
 
 	/*
 	 * double map exception vectors at top of virtual memory
--- /sys/src/9/bcm/fns.h	Sun Jan  3 20:07:55 2016
+++ /sys/src/9/bcm/fns.h	Sun Jan  3 20:07:56 2016
@@ -55,7 +55,7 @@
 extern int l2ap(int);
 extern void l2cachewbinv(void);
 extern void links(void);
-extern void mmuinit(void);
+extern void mmuinit(void*);
 extern void mmuinit1(void*);
 extern void mmuinvalidate(void);
 extern void mmuinvalidateaddr(u32int);
--- /sys/src/9/bcm/armv6.s	Sun Jan  3 20:07:58 2016
+++ /sys/src/9/bcm/armv6.s	Sun Jan  3 20:07:59 2016
@@ -20,16 +20,6 @@
 	MCR	CpSC, 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinv
 	ISB
 
-	/* ACT LED on */
-	MOVW	$0x20200014,R2
-	MOVW	(R2),R3
-	AND		$~(7<<21),R3
-	ORR		$(1<<21),R3
-	MOVW	R3,(R2)
-	MOVW	$0x20200020,R2
-	MOVW	$0x8000,R3
-	MOVW	R3,(R2)
-
 	/*
 	 * clear mach and page tables
 	 */
@@ -46,6 +36,7 @@
 	 * set up page tables for kernel
 	 */
 	MOVW	$PADDR(MACHADDR+MACHSIZE-4), R13
+	MOVW	$PADDR(L1), R0
 	BL	,mmuinit(SB)
 
 	/*
@@ -87,6 +78,10 @@
 
 	BL	_div(SB)		/* hack to load _div, etc. */
 
+TEXT cpidget(SB), 1, $-4			/* main ID */
+	MRC	CpSC, 0, R0, C(CpID), C(0), CpIDid
+	RET
+
 TEXT fsrget(SB), 1, $-4				/* data fault status */
 	MRC	CpSC, 0, R0, C(CpFSR), C(0), CpFSRdata
 	RET
@@ -103,6 +98,12 @@
 	MRC	CpSC, 0, R0, C(CpSPM), C(CpSPMperf), CpSPMcyc
 	RET
 
+TEXT tmrget(SB), 1, $-4				/* local generic timer physical counter value */
+	MOVW	$0, R1				/* not in armv6 */
+	MOVW	R1, 0(R0)
+	MOVW	R1, 4(R0)
+	RET
+
 TEXT splhi(SB), 1, $-4
 	MOVW	$(MACHADDR+4), R2		/* save caller pc in Mach */
 	MOVW	R14, 0(R2)
@@ -175,14 +176,15 @@
 	RET
 
 TEXT idlehands(SB), $-4
-	BARRIERS
 	MOVW	CPSR, R3
-	BIC	$(PsrDirq|PsrDfiq), R3, R1		/* spllo */
+	ORR	$(PsrDirq|PsrDfiq), R3, R1		/* splfhi */
 	MOVW	R1, CPSR
 
-	MOVW	$0, R0				/* wait for interrupt */
-	MCR	CpSC, 0, R0, C(CpCACHE), C(CpCACHEintr), CpCACHEwait
-	ISB
+	DSB
+	MOVW	nrdy(SB), R0
+	CMP	$0, R0
+	MCR.EQ	CpSC, 0, R0, C(CpCACHE), C(CpCACHEintr), CpCACHEwait
+	DSB
 
 	MOVW	R3, CPSR			/* splx */
 	RET