add the soc structure to differentiate the pi and pi2

Reference: /n/atom/patch/applied/pi2soc
Date: Sun Jan  3 06:15:06 CET 2016
Signed-off-by: quanstro@quanstro.net

--- /sys/src/9/bcm/archbcm.c	Sun Jan  3 06:14:25 2016
+++ /sys/src/9/bcm/archbcm.c	Sun Jan  3 06:14:26 2016
@@ -1,5 +1,5 @@
 /*
- * bcm2835 (e.g. raspberry pi) architecture-specific stuff
+ * bcm2835 (e.g. original raspberry pi) architecture-specific stuff
  */
 
 #include "u.h"
@@ -16,6 +16,13 @@
 
 #define	POWERREGS	(VIRTIO+0x100000)
 
+Soc soc = {
+	.dramsize	= 512*MiB,
+	.physio		= 0x20000000,
+	.busdram	= 0x40000000,
+	.busio		= 0x7E000000,
+};
+
 enum {
 	Wdogfreq	= 65536,
 	Wdogtime	= 5,	/* seconds, ≤ 15 */
@@ -71,10 +78,21 @@
 	r[Rstc] = Password | (r[Rstc] & ~CfgMask);
 }
 	
+char *
+cputype2name(char *buf, int size)
+{
+	seprint(buf, buf + size, "1176JZF-S");
+	return buf;
+}
+
 void
 cpuidprint(void)
 {
-	print("cpu%d: %dMHz ARM1176JZF-S\n", m->machno, m->cpumhz);
+	char name[64];
+
+	cputype2name(name, sizeof name);
+	delay(50);				/* let uart catch up */
+	print("cpu%d: %dMHz ARM %s\n", m->machno, m->cpumhz, name);
 }
 
 void
@@ -98,3 +116,8 @@
 	return -1;
 }
 
+int
+l2ap(int ap)
+{
+	return (AP(3, (ap))|AP(2, (ap))|AP(1, (ap))|AP(0, (ap)));
+}
--- /sys/src/9/bcm/archbcm2.c	Thu Jan  1 00:00:00 1970
+++ /sys/src/9/bcm/archbcm2.c	Sun Jan  3 06:14:27 2016
@@ -0,0 +1,128 @@
+/*
+ * bcm2836 (e.g.raspberry pi 2) architecture-specific stuff
+ */
+
+#include "u.h"
+#include "../port/lib.h"
+#include "mem.h"
+#include "dat.h"
+#include "fns.h"
+#include "../port/error.h"
+#include "io.h"
+#include "arm.h"
+
+#include "../port/netif.h"
+#include "etherif.h"
+
+#define	POWERREGS	(VIRTIO+0x100000)
+
+Soc soc = {
+	.dramsize	= 1024*MiB,
+	.physio		= 0x3F000000,
+	.busdram	= 0xC0000000,
+	.busio		= 0x7E000000,
+};
+
+enum {
+	Wdogfreq	= 65536,
+	Wdogtime	= 5,	/* seconds, ≤ 15 */
+};
+
+/*
+ * Power management / watchdog registers
+ */
+enum {
+	Rstc		= 0x1c>>2,
+		Password	= 0x5A<<24,
+		CfgMask		= 0x03<<4,
+		CfgReset	= 0x02<<4,
+	Rsts		= 0x20>>2,
+	Wdog		= 0x24>>2,
+};
+
+void
+archreset(void)
+{
+	fpon();
+}
+
+void
+archreboot(void)
+{
+	u32int *r;
+
+	r = (u32int*)POWERREGS;
+	r[Wdog] = Password | 1;
+	r[Rstc] = Password | (r[Rstc] & ~CfgMask) | CfgReset;
+	coherence();
+	for(;;)
+		;
+}
+
+static void
+wdogfeed(void)
+{
+	u32int *r;
+
+	r = (u32int*)POWERREGS;
+	r[Wdog] = Password | (Wdogtime * Wdogfreq);
+	r[Rstc] = Password | (r[Rstc] & ~CfgMask) | CfgReset;
+}
+
+void
+wdogoff(void)
+{
+	u32int *r;
+
+	r = (u32int*)POWERREGS;
+	r[Rstc] = Password | (r[Rstc] & ~CfgMask);
+}
+	
+char *
+cputype2name(char *buf, int size)
+{
+	ulong r;
+
+	r = cpidget();			/* main id register */
+	assert((r >> 24) == 'A');
+	seprint(buf, buf + size, "Cortex-A7 r%ldp%ld",
+		(r >> 20) & MASK(4), r & MASK(4));
+	return buf;
+}
+
+void
+cpuidprint(void)
+{
+	char name[64];
+
+	cputype2name(name, sizeof name);
+	delay(50);				/* let uart catch up */
+	print("cpu%d: %dMHz ARM %s\n", m->machno, m->cpumhz, name);
+}
+
+void
+archbcm2link(void)
+{
+	addclock0link(wdogfeed, HZ);
+}
+
+int
+archether(unsigned ctlrno, Ether *ether)
+{
+	switch(ctlrno) {
+	case 0:
+		ether->type = "usb";
+		ether->ctlrno = ctlrno;
+		ether->irq = -1;
+		ether->nopt = 0;
+		ether->mbps = 100;
+		return 1;
+	}
+	return -1;
+}
+
+int
+l2ap(int ap)
+{
+	return (AP(0, (ap)));
+}
--- /sys/src/9/bcm/dat.h	Sun Jan  3 06:14:29 2016
+++ /sys/src/9/bcm/dat.h	Sun Jan  3 06:14:30 2016
@@ -29,6 +29,7 @@
 typedef struct PMMU	PMMU;
 typedef struct Proc	Proc;
 typedef u32int		PTE;
+typedef struct Soc	Soc;
 typedef struct Uart	Uart;
 typedef struct Ureg	Ureg;
 typedef uvlong		Tval;
@@ -289,3 +290,10 @@
 	Devport	*ports;			/* The ports themselves */
 };
 
+struct Soc {			/* SoC dependent configuration */
+	ulong	dramsize;
+	uintptr	physio;
+	uintptr	busdram;
+	uintptr	busio;
+};
+extern Soc soc;