additional bits required for updating trap.c and dma.c

Reference: /n/atom/patch/applied/pi2bits
Date: Sun Jan  3 08:40:03 CET 2016
Signed-off-by: quanstro@quanstro.net

--- /sys/src/9/bcm/archbcm.c	Sun Jan  3 08:39:24 2016
+++ /sys/src/9/bcm/archbcm.c	Sun Jan  3 08:39:25 2016
@@ -21,6 +21,9 @@
 	.physio		= 0x20000000,
 	.busdram	= 0x40000000,
 	.busio		= 0x7E000000,
+	.armlocal	= 0,
+	.l1ptedramattrs = Cached | Buffered,
+	.l2ptedramattrs = Cached | Buffered,
 };
 
 enum {
--- /sys/src/9/bcm/cache.v7.s	Sun Jan  3 08:39:27 2016
+++ /sys/src/9/bcm/cache.v7.s	Sun Jan  3 08:39:28 2016
@@ -137,8 +137,6 @@
 	BIC	$KSEGM,	R1	/* strip segment from address */
 	MOVW	PC, R2		/* get PC's segment ... */
 	AND	$KSEGM, R2
-	CMP	$0, R2		/* PC segment should be non-zero on omap */
-	BEQ	buggery
 	ORR	R2, R1		/* combine them */
 
 	/* drain write buffers */
@@ -199,10 +197,4 @@
 	/* drain write buffers */
 	MCR	CpSC, 0, R0, C(CpCACHE), C(CpCACHEwb), CpCACHEwait
 	ISB
-	RET
-
-buggery:
-PUTC('?')
-	MOVW	PC, R0
-//	B	pczeroseg(SB)
 	RET
--- /sys/src/9/bcm/mem.h	Sun Jan  3 08:39:30 2016
+++ /sys/src/9/bcm/mem.h	Sun Jan  3 08:39:31 2016
@@ -22,6 +22,7 @@
 
 #define	MAXMACH		4			/* max # cpus system can run */
 #define	MACHSIZE	BY2PG
+#define L1SIZE		(4 * BY2PG)
 
 #define KSTKSIZE	(8*KiB)
 #define STACKALIGN(sp)	((sp) & ~3)		/* bug: assure with alloc */
@@ -65,7 +66,7 @@
 #define	TSTKSIZ	 	256
 
 /* address at which to copy and execute rebootcode */
-#define	REBOOTADDR	(KZERO+0x3400)
+#define	REBOOTADDR	(KZERO+0x1800)
 
 /*
  * Legacy...
--- /sys/src/9/bcm/io.h	Sun Jan  3 08:39:33 2016
+++ /sys/src/9/bcm/io.h	Sun Jan  3 08:39:35 2016
@@ -8,11 +8,17 @@
 	IRQdma0		= 16,
 #define IRQDMA(chan)	(IRQdma0+(chan))
 	IRQaux		= 29,
+	IRQi2c		= 53,
+	IRQspi		= 54,
 	IRQmmc		= 62,
 
 	IRQbasic	= 64,
 	IRQtimerArm	= IRQbasic + 0,
 
+	IRQlocal	= 96,
+	IRQcntps	= IRQlocal + 0,
+	IRQcntpns	= IRQlocal + 1,
+
 	IRQfiq		= IRQusb,	/* only one source can be FIQ */
 
 	DmaD2M		= 0,		/* device to memory */
@@ -20,6 +26,11 @@
 	DmaM2M		= 2,		/* memory to memory */
 
 	DmaChanEmmc	= 4,		/* can only use 2-5, maybe 0 */
+	DmaChanSpiTx= 2,
+	DmaChanSpiRx= 0,
+
+	DmaDevSpiTx	= 6,
+	DmaDevSpiRx	= 7,
 	DmaDevEmmc	= 11,
 
 	PowerSd		= 0,
--- /sys/src/9/bcm/fns.h	Sun Jan  3 08:39:37 2016
+++ /sys/src/9/bcm/fns.h	Sun Jan  3 08:39:38 2016
@@ -53,6 +53,7 @@
 #define intrenable(i, f, a, b, n) irqenable((i), (f), (a))
 extern void intrsoff(void);
 extern int l2ap(int);
+extern void l2cachewbinv(void);
 extern void links(void);
 extern void mmuinit(void);
 extern void mmuinit1(void);
--- /sys/src/9/bcm/devarch.c	Sun Jan  3 08:39:40 2016
+++ /sys/src/9/bcm/devarch.c	Sun Jan  3 08:39:41 2016
@@ -160,7 +160,8 @@
 static long
 cputempread(Chan*, void *a, long n, vlong offset)
 {
-	char str[128];
+	char str[16];
+
 	snprint(str, sizeof str, "%d±%d\n", gettemp(TempCpu) / 1000, 1);
 	return readstr(offset, a, n, str);
 }
@@ -169,5 +170,5 @@
 archinit(void)
 {
 	addarchfile("cputype", 0444, cputyperead, nil);
-	addarchfile("cputemp", 0444, cputempread, nil); 
+	addarchfile("cputemp", 0444, cputempread, nil);
 }
--- /sys/src/9/bcm/armv6.s	Sun Jan  3 08:39:43 2016
+++ /sys/src/9/bcm/armv6.s	Sun Jan  3 08:39:44 2016
@@ -4,6 +4,7 @@
  */
 
 #include "arm.s"
+
 #define CACHELINESZ 32
 
 TEXT armstart(SB), 1, $-4
@@ -211,6 +212,16 @@
 
 /*
  * drain write buffer
+ * writeback data cache
+ */
+TEXT cachedwb(SB), 1, $-4
+	DSB
+	MOVW	$0, R0
+	MCR	CpSC, 0, R0, C(CpCACHE), C(CpCACHEwb), CpCACHEall
+	RET
+
+/*
+ * drain write buffer
  * writeback and invalidate data cache
  */
 TEXT cachedwbinv(SB), 1, $-4
@@ -248,6 +259,22 @@
 	BIC	$(CACHELINESZ-1), R1
 	BIC	$(CACHELINESZ-1), R2
 	MCRR(CpSC, 0, 2, 1, CpCACHERANGEdwb)
+	RET
+
+/*
+ * cachedinvse(va, n)
+ *   drain write buffer
+ *   invalidate data cache range [va, va+n)
+ */
+TEXT cachedinvse(SB), 1, $-4
+	MOVW	R0, R1		/* DSB clears R0 */
+	DSB
+	MOVW	n+4(FP), R2
+	ADD	R1, R2
+	SUB	$1, R2
+	BIC	$(CACHELINESZ-1), R1
+	BIC	$(CACHELINESZ-1), R2
+	MCRR(CpSC, 0, 2, 1, CpCACHERANGEinvd)
 	RET
 
 /*