create processor-local, single (4k) page mapping for use with acpiio.

Reference: /n/atom/patch/applied/nixtmpmap
Date: Mon Mar 10 15:07:22 CET 2014
Signed-off-by: quanstro@quanstro.net

--- /sys/src/nix/k10/mmu.c	Mon Mar 10 15:06:48 2014
+++ /sys/src/nix/k10/mmu.c	Mon Mar 10 15:06:50 2014
@@ -738,6 +738,49 @@
 	DBG("vunmap(%#p, %lud)\n", v, size);
 }
 
+enum {
+	Tmpaddr		= KSEG2END,
+};
+
+/* processor-local single 4k page map */
+void*
+tmpmap(uintmem pa)
+{
+	usize o;
+	PTE *pml4, *pte;
+	Mpl pl;
+
+	DBG("%d: tmpmap(%#P, )\n", m->machno, pa);
+	o = pa & ((1<<PGSHIFT)-1);
+	pa -= o;
+
+	pml4 = UINT2PTR(m->pml4->va);
+	pl = splhi();
+	if(mmuwalk(pml4, Tmpaddr, 0, &pte, walkalloc) < 0)
+		panic("mmu: tmpmap: mmuwalk");
+	*pte = pa | memflagssz(PteP|PteRW, PGLSZ(0));
+	invlpg(Tmpaddr);			/* forgot to unmap?  error? */
+	splx(pl);
+
+	DBG("%d: tmpmap(%#P) → %#p + %lux\n", m->machno, pa, Tmpaddr, o);
+	return UINT2PTR(Tmpaddr + o);
+}
+
+void
+tmpunmap(void*)
+{
+	PTE *pml4, *pte;
+	Mpl pl;
+
+	pml4 = UINT2PTR(m->pml4->va);
+	pl = splhi();
+	if(mmuwalk(pml4, Tmpaddr, 0, &pte, nil) < 0)
+		panic("mmu: tmpmap: mmuwalk");
+	*pte = 0;
+	invlpg(Tmpaddr);
+	splx(pl);
+}
+
 int
 mmuwalk(PTE* pml4, uintptr va, int level, PTE** ret, uintmem (*alloc)(usize))
 {
--- /sys/src/nix/k10/fns.h	Mon Mar 10 15:06:51 2014
+++ /sys/src/nix/k10/fns.h	Mon Mar 10 15:06:52 2014
@@ -31,9 +31,15 @@
 void	fpuprocrestore(Proc*);
 void	fpuprocsave(Proc*);
 void	fpusysprocsetup(Proc*);
-void	fpusysrforkchild(Proc*, Proc*);
 void	fpusysrfork(Ureg*);
+void	fpusysrforkchild(Proc*, Proc*);
+void	gdtget(void*);
+void	gdtput(int, u64int, u16int);
 char*	getconf(char*);
+u64int	getcr0(void);
+u64int	getcr2(void);
+u64int	getcr3(void);
+u64int	getcr4(void);
 void	halt(void);
 void	hardhalt(void);
 int	i8042auxcmd(int);
@@ -44,6 +50,7 @@
 void	i8250console(void);
 void	idlehands(void);
 void	idthandlers(void);
+void	idtput(int, u64int);
 int	inb(int);
 u32int	inl(int);
 void	insb(int, void*, int);
@@ -89,36 +96,32 @@
 void	pause(void);
 void	physallocdump(void);
 void	printcpufreq(void);
+void	putcr0(u64int);
+void	putcr3(u64int);
+void	putcr4(u64int);
+u64int	rdmsr(u32int);
+void	rdrandbuf(void*, usize);
+u64int	rdtsc(void);
 int	screenprint(char*, ...);			/* debugging */
 void	sfence(void);
 void	syscall(uint, Ureg*);
+void*	tmpmap(uintmem);
+void	tmpunmap(void*);
+void	trap(Ureg*);
 void	trapenable(int, void (*)(Ureg*, void*), void*, char*);
 void	trapinit(void);
-void	trap(Ureg*);
+void	trput(u64int);
 void	tssrsp0(u64int);
 void	umeminit(void);
 int	userureg(Ureg*);
-void*	vmap(uintmem, usize);
-void*	vmappat(uintmem, usize, uint);
+void	vctlinit(Vctl*);
+void*	vintrenable(Vctl*, char*);
 void*	vmapoverlap(uintmem, usize);
+void*	vmappat(uintmem, usize, uint);
 int	vmapsync(uintptr);
+void*	vmap(uintmem, usize);
 void	vsvminit(int);
 void	vunmap(void*, usize);
-
-u64int	getcr0(void);
-void	putcr0(u64int);
-u64int	getcr2(void);
-u64int	getcr3(void);
-void	putcr3(u64int);
-u64int	getcr4(void);
-void	putcr4(u64int);
-void	gdtget(void*);
-void	gdtput(int, u64int, u16int);
-void	idtput(int, u64int);
-u64int	rdmsr(u32int);
-void	rdrandbuf(void*, usize);
-u64int	rdtsc(void);
-void	trput(u64int);
 void	writeconf(void);
 void	wrmsr(u32int, u64int);