break out the ioapicrdt logic so we can more clealy seperate isa and pci
interrupt sources

Reference: /n/atom/patch/applied/ioapicmsixprep
Date: Sun Aug 16 19:49:34 CES 2015
Signed-off-by: quanstro@quanstro.net

--- /sys/src/nix/k10/ioapic.c	Sun Aug 16 19:48:27 2015
+++ /sys/src/nix/k10/ioapic.c	Sun Aug 16 19:48:29 2015
@@ -469,51 +469,11 @@
 }
 
 int
-ioapicintrenable(Vctl* v)
+ioapicrdt(Vctl *v, int busno, int devno, int bustype)
 {
-	Pcidev *p;
+	u32int hi, lo;
 	Rbus *rbus;
 	Rdt *rdt;
-	u32int hi, lo;
-	int bustype, busno, devno;
-
-	if(v->tbdf == BUSUNKNOWN){
-		if(v->irq >= IrqLINT0 && v->irq <= MaxIrqLAPIC){
-			if(v->irq != IrqSPURIOUS)
-				v->isr = lapiceoi;
-			v->type = "lapic";
-			return v->irq;
-		}
-		else{
-			/*
-			 * Legacy ISA.
-			 * Make a busno and devno using the
-			 * ISA bus number and the irq.
-			 */
-			if(isabusno == -1)
-				panic("no ISA bus allocated");
-			busno = isabusno;
-			devno = v->irq;
-			bustype = BusISA;
-		}
-	}
-	else if((bustype = BUSTYPE(v->tbdf)) == BusPCI){
-		busno = BUSBNO(v->tbdf);
-		if((p = pcimatchtbdf(v->tbdf)) == nil)
-			panic("ioapic: no pci dev for tbdf %T", v->tbdf);
-		if(intrenablemsi(v, p) != -1)
-			return v->vno;
-		disablemsi(v, p);
-		if((devno = pcicfgr8(p, PciINTP)) == 0)
-			panic("no INTP for tbdf %T", v->tbdf);
-		devno = BUSDNO(v->tbdf)<<2|(devno-1);
-		DBG("ioapicintrenable: tbdf %T busno %d devno %d\n",
-			v->tbdf, busno, devno);
-	}
-	else{
-		SET(busno, devno);
-		panic("unknown tbdf %T", v->tbdf);
-	}
 
 	rdt = nil;
 	for(rbus = rdtbus[busno]; rbus != nil; rbus = rbus->next)
@@ -551,9 +511,9 @@
 
 	lock(rdt->apic);
 	ainc(&rdt->enabled);
-	lo = (rdt->lo & ~Im);
 
 	if((rdt->lo & 0xff) == 0){
+		lo = (rdt->lo & ~Im);
 		ioapicphysdd(v, &hi, &lo);
 		rdt->lo |= lo & 0xff;
 		rdt->vec = (u64int)hi<<32 | lo;
@@ -575,6 +535,49 @@
 	v->type = "ioapic";
 
 	return v->vno;
+}
+
+int
+ioapicintrenable(Vctl* v)
+{
+	int devno;
+	Pcidev *p;
+
+	if(v->tbdf == BUSUNKNOWN){
+		if(v->irq >= IrqLINT0 && v->irq <= MaxIrqLAPIC){
+			if(v->irq != IrqSPURIOUS)
+				v->isr = lapiceoi;
+			v->type = "lapic";
+			return v->irq;
+		}
+		else{
+			/*
+			 * Legacy ISA.
+			 * Make a busno and devno using the
+			 * ISA bus number and the irq.
+			 */
+			if(isabusno == -1)
+				panic("no ISA bus allocated");
+			return ioapicrdt(v, isabusno, v->irq, BusISA);
+		}
+	}
+	else if(BUSTYPE(v->tbdf) == BusPCI){
+		/* BOTCH msi is in the wrong place.  it has nothing to do with ioapics */
+		if((p = pcimatchtbdf(v->tbdf)) == nil)
+			panic("ioapic: no pci dev for tbdf %T", v->tbdf);
+		if(intrenablemsi(v, p) != -1)
+			return v->vno;
+		disablemsi(v, p);
+		if((devno = pcicfgr8(p, PciINTP)) == 0){
+			print("ioapicintrenable: no intp for %T\n", v->tbdf);
+			return -1;
+		}
+		return ioapicrdt(v, BUSBNO(v->tbdf), BUSDNO(v->tbdf)<<2|(devno-1), BusPCI);
+	}
+	else{
+		panic("unknown tbdf %T", v->tbdf);
+		return -1;
+	}
 }
 
 int