the interrupt delays in vbox differ quite a bit from real hardware.  on
real hardware the delays are not perceptable, but on vbox this can result
in local ping times of 55ms.  also improve the messages for adapters which
aren't going to work yet.

Reference: /n/atom/patch/applied/igbevboxspeedup
Date: Tue Apr 22 15:40:30 CES 2014
Signed-off-by: quanstro@quanstro.net

--- /sys/src/nix/k10/etherigbe.c	Tue Apr 22 15:38:43 2014
+++ /sys/src/nix/k10/etherigbe.c	Tue Apr 22 15:38:43 2014
@@ -433,7 +433,8 @@
 enum {
 	Nrd		= 256,		/* multiple of 8 */
 	Ntd		= 64,		/* multiple of 8 */
-	Nrb		= 512,		/* private receive buffers per Ctlr */
+	Nrb		= 1024,		/* private receive buffers per Ctlr */
+	Rbalign		= 64,
 	Rbsz		= 9*1024+128,
 	Rbsize		= Bsize16384|Bsex|Lpe,
 };
@@ -509,7 +510,6 @@
 #define csr32w(c, r, v)	(*((c)->nic+((r)/4)) = (v))
 
 static Ctlr* igbectlrhead;
-static Ctlr* igbectlrtail;
 
 static Lock igberblock;		/* free receive Blocks */
 static Block* igberbpool;	/* receive Blocks for all igbe controllers */
@@ -758,7 +758,7 @@
 static void
 igberbfree(Block* b)
 {
-	b->rp = b->wp = (uchar*)ROUNDUP((uintptr)b->base, PGSZ);
+	b->rp = b->wp = (uchar*)ROUNDUP(PTR2UINT(b->base), Rbalign);
 	b->flag &= ~(Bipck | Budpck | Btcpck | Bpktck);
 	ilock(&igberblock);
 	b->next = igberbpool;
@@ -940,14 +940,13 @@
 		r &= ~WthreshMASK;
 		r |= Gran|(4<<WthreshSHIFT);
 
-		csr32w(ctlr, Tadv, 64);
+		csr32w(ctlr, Tadv, 0);
 		break;
 	}
 
 	csr32w(ctlr, Txdctl, r);
 
-	r = csr32r(ctlr, Tctl);
-	r |= Ten;
+	r = csr32r(ctlr, Tctl) | Ten;
 	csr32w(ctlr, Tctl, r);
 }
 
@@ -1085,7 +1084,7 @@
 	case i82546gb:
 	case i82546eb:
 	case i82547gi:
-		csr32w(ctlr, Radv, 64);
+		csr32w(ctlr, Radv, 0);
 		break;
 	}
 	csr32w(ctlr, Rxdctl, (8<<WthreshSHIFT)|(8<<HthreshSHIFT)|4);
@@ -1178,7 +1177,7 @@
 		}
 		ctlr->rdh = rdh;
 
-		if(ctlr->rdfree < ctlr->nrd/2 || (ctlr->rim & Rxdmt0))
+		if(ctlr->rdfree >= 32 || (ctlr->rim & Rxdmt0))
 			igbereplenish(ctlr);
 	}
 }
@@ -1252,7 +1251,7 @@
 	}
 
 	for(i = 0; i < Nrb; i++){
-		bp = allocb(Rbsz+PGSZ);
+		bp = allocb(Rbsz+Rbalign);
 		bp->free = igberbfree;
 		freeb(bp);
 	}
@@ -1459,8 +1458,10 @@
 	int (*write)(Mii*, int, int, int);
 
 	r = csr32r(ctlr, Status);
-	if(r & Tbimode)
+	if(r & Tbimode){
+		print("etherigbe: %T: mii: tbimode unsupported\n", ctlr->pcidev->tbdf);
 		return -1;
+	}
 
 	ctrl = csr32r(ctlr, Ctrl);
 	ctrl |= Slu;
@@ -1477,8 +1478,10 @@
 		 * so bail.
 		 */
 		r = csr32r(ctlr, Ctrlext);
-		if(!(r & Mdro))
+		if(!(r & Mdro)){
+			print("etherigbe: %T: Mdro driver bug\n", ctlr->pcidev->tbdf);
 			return -1;
+		}
 		csr32w(ctlr, Ctrlext, r);
 		delay(20);
 		r = csr32r(ctlr, Ctrlext);
@@ -1514,12 +1517,13 @@
 		write = igbemiimiw;
 		break;
 	default:
+		print("igbe: mii: unknown: %.8ux\n", ctlr->id);
 		return -1;
 	}
 
 	if((ctlr->mii = miiattach(ctlr, ~0, read, write)) == nil)
 		return -1;
-	// print("oui %X phyno %d\n", ctlr->mii->curphy->oui, ctlr->mii->curphy->phyno);
+	// print("oui %x phyno %d\n", ctlr->mii->curphy->oui, ctlr->mii->curphy->phyno);
 
 	/*
 	 * 8254X-specific PHY registers not in 802.3:
@@ -1909,7 +1913,6 @@
 		csr32w(ctlr, Txcw, txcw);
 	}
 
-
 	/*
 	 * Flow control - values from the datasheet.
 	 */
@@ -1921,8 +1924,10 @@
 	csr32w(ctlr, Fcrtl, ctlr->fcrtl);
 	csr32w(ctlr, Fcrth, ctlr->fcrth);
 
-	if(!(csr32r(ctlr, Status) & Tbimode) && igbemii(ctlr) < 0)
+	if(!(csr32r(ctlr, Status) & Tbimode) && igbemii(ctlr) < 0){
+		print("igbe: %T mii fails\n", ctlr->pcidev->tbdf);
 		return -1;
+	}
 
 	return 0;
 }
@@ -1932,9 +1937,10 @@
 {
 	int cls;
 	Pcidev *p;
-	Ctlr *ctlr;
+	Ctlr *ctlr, **cc;
 	void *mem;
 
+	cc = &igbectlrhead;
 	for(p = nil; p = pcimatch(p, 0, 0); ){
 		if(p->ccrb != 0x02 || p->ccru != 0)
 			continue;
@@ -1998,12 +2004,8 @@
 			continue;
 		}
 		pcisetbme(p);
-
-		if(igbectlrhead != nil)
-			igbectlrtail->next = ctlr;
-		else
-			igbectlrhead = ctlr;
-		igbectlrtail = ctlr;
+		*cc = ctlr;
+		cc = &ctlr->next;
 	}
 }