add speculative support for the rangeley c2000 onboard nics.
i'm not sure if the phy support is right.  we may need to poke
@ the marvell alaska phy by hand.  hopefully it will pass traffic,
even if link is not properly detected.

Reference: /n/atom/patch/applied/i354
Date: Mon May 26 21:24:17 CES 2014
Signed-off-by: quanstro@quanstro.net

--- /sys/src/nix/k10/ether82563.c	Mon May 26 21:23:07 2014
+++ /sys/src/nix/k10/ether82563.c	Mon May 26 21:23:10 2014
@@ -1,5 +1,5 @@
 /*
- * Intel 8256[367], 8257[1-9], 8258[03], i21[01], i350
+ * Intel 8256[367], 8257[1-9], 8258[03], i21[01], i350, i354
  *	Gigabit Ethernet PCI-Express Controllers
  * Coraid EtherDrive® hba
  */
@@ -449,6 +449,7 @@
 	i210,
 	i217,
 	i350,
+	i354,
 	Nctlrtype,
 };
 
@@ -492,6 +493,7 @@
 	i210,		9728,	1,	"i210",		F75|Fnofct|Fert,
 	i217,		9728,	1,	"i217",		F79phy|Fnofct|Fload|Fert,
 	i350,		9728,	1,	"i350",		F75|F79phy|Fnofct,
+	i354,		9728,	1,	"i350",		F75|F79phy|Fnofct,
 };
 
 typedef void (*Freefn)(Block*);
@@ -1756,7 +1758,7 @@
 static int
 fload(Ctlr *c)
 {
-	uint data,  r, adr;
+	uint data, r, adr;
 	u16int sum;
 	uintmem io;
 	Flash f;
@@ -2004,6 +2006,11 @@
 	case 0x1523:		/* serdes */
 	case 0x1524:		/* sgmii */
 		return i350;
+	case 0x1f40:		/* backplane */
+	case 0x1f41:		/* sgmii */
+	case 0x1f42:		/* sgmii (c2000) */
+	case 0x1f45:		/* backplane 2.5 */
+		return i354:
 	}
 	return -1;
 }
--- /sys/src/9/pc/ether82563.c	Mon May 26 21:23:13 2014
+++ /sys/src/9/pc/ether82563.c	Mon May 26 21:23:16 2014
@@ -1,5 +1,5 @@
 /*
- * Intel 8256[367], 8257[1-9], 8258[03], i21[01], i350
+ * Intel 8256[367], 8257[1-9], 8258[03], i21[01], i350, i354
  *	Gigabit Ethernet PCI-Express Controllers
  * Coraid EtherDrive® hba
  */
@@ -31,7 +31,7 @@
 	Fla		= 0x001c,	/* Flash Access */
 	Mdic		= 0x0020,	/* MDI Control */
 	Fcal		= 0x0028,	/* Flow Control Address Low */
-	Fcah		= 0x002C,	/* Flow Control Address High */
+	Fcah		= 0x002c,	/* Flow Control Address High */
 	Fct		= 0x0030,	/* Flow Control Type */
 	Kumctrlsta	= 0x0034,	/* Kumeran Control and Status Register */
 	Connsw		= 0x0034,	/* copper / fiber switch control; 82575/82576 */
@@ -39,19 +39,22 @@
 	Fcttv		= 0x0170,	/* Flow Control Transmit Timer Value */
 	Txcw		= 0x0178,	/* Transmit Configuration Word */
 	Rxcw		= 0x0180,	/* Receive Configuration Word */
-	Ledctl		= 0x0E00,	/* LED control */
+	Ledctl		= 0x0e00,	/* LED control */
 	Pba		= 0x1000,	/* Packet Buffer Allocation */
 	Pbs		= 0x1008,	/* Packet Buffer Size */
 
 	/* Interrupt */
 
-	Icr		= 0x00C0,	/* Interrupt Cause Read */
+	Icr		= 0x00c0,	/* Interrupt Cause Read */
 	Itr		= 0x00c4,	/* Interrupt Throttling Rate */
-	Ics		= 0x00C8,	/* Interrupt Cause Set */
-	Ims		= 0x00D0,	/* Interrupt Mask Set/Read */
-	Imc		= 0x00D8,	/* Interrupt mask Clear */
-	Iam		= 0x00E0,	/* Interrupt acknowledge Auto Mask */
+	Ics		= 0x00c8,	/* Interrupt Cause Set */
+	Ims		= 0x00d0,	/* Interrupt Mask Set/Read */
+	Imc		= 0x00d8,	/* Interrupt mask Clear */
+	Iam		= 0x00e0,	/* Interrupt acknowledge Auto Mask */
+	Ivar		= 0x00e4,	/* Ivar: interrupt allocation */
 	Eitr		= 0x1680,	/* Extended itr; 82575/6 80 only */
+	P3gio		= 0x5b00,	/*  */
+	Pbaclr		= 0x5b68,	/* clear msi-x pba */
 
 	/* Receive */
 
@@ -143,6 +146,9 @@
 	Internalphy	= 0<<22,	/* " internal phy (copper) */
 	Sgmii		= 2<<22,	/* " sgmii */
 	Serdes		= 3<<22,	/* " serdes */
+	Eiame		= 1<<24,	/* extended auto mask enable */
+	Iame		= 1<<27,	/* auto mask enable */
+	Pbasup		= 1<<31,	/* msi-x pba support */
 };
 
 enum {
@@ -443,6 +449,7 @@
 	i210,
 	i217,
 	i350,
+	i354,
 	Nctlrtype,
 };
 
@@ -483,9 +490,10 @@
 	i82579,		9018,	2,	"i82579",		Fload|Fert|F79phy|Fnofct,
 	i82580,		9728,	1,	"i82580",		F75|F79phy,
 	i82583,		1514,	1,	"i82583",		0,
-	i210,		9728,	1,	"i210",		F75|F79phy|Fnofct|Fert,
+	i210,		9728,	1,	"i210",		F75|Fnofct|Fert,
 	i217,		9728,	1,	"i217",		F79phy|Fnofct|Fload|Fert,
 	i350,		9728,	1,	"i350",		F75|F79phy|Fnofct,
+	i354,		9728,	1,	"i350",		F75|F79phy|Fnofct,
 };
 
 typedef void (*Freefn)(Block*);
@@ -1417,6 +1425,7 @@
 		case i82578:
 		case i82578m:
 		case i82583:
+		case i210:
 			a = phyread(c, phyno, Phyisr) & Ane;
 			break;
 		case i82571:
@@ -1749,7 +1758,7 @@
 static int
 fload(Ctlr *c)
 {
-	uint data,  r, adr;
+	uint data, r, adr;
 	u16int sum;
 	uintmem io;
 	Flash f;
@@ -1997,6 +2006,11 @@
 	case 0x1523:		/* serdes */
 	case 0x1524:		/* sgmii */
 		return i350;
+	case 0x1f40:		/* backplane */
+	case 0x1f41:		/* sgmii */
+	case 0x1f42:		/* sgmii (c2000) */
+	case 0x1f45:		/* backplane 2.5 */
+		return i354:
 	}
 	return -1;
 }
@@ -2048,11 +2062,11 @@
 		print("%s: can't map %#P\n", cname(ctlr), ctlr->port);
 		return -1;
 	}
+	pcisetbme(p);
 	if(i82563reset(ctlr)){
 		vunmap(ctlr->nic, p->mem[0].size);
 		return -1;
 	}
-	pcisetbme(ctlr->pcidev);
 	return 0;
 }
 
--- /sys/src/9/pcpae/ether82563.c	Mon May 26 21:23:19 2014
+++ /sys/src/9/pcpae/ether82563.c	Mon May 26 21:23:21 2014
@@ -1,5 +1,5 @@
 /*
- * Intel 8256[367], 8257[1-9], 8258[03], i21[01], i350
+ * Intel 8256[367], 8257[1-9], 8258[03], i21[01], i350, i354
  *	Gigabit Ethernet PCI-Express Controllers
  * Coraid EtherDrive® hba
  */
@@ -31,7 +31,7 @@
 	Fla		= 0x001c,	/* Flash Access */
 	Mdic		= 0x0020,	/* MDI Control */
 	Fcal		= 0x0028,	/* Flow Control Address Low */
-	Fcah		= 0x002C,	/* Flow Control Address High */
+	Fcah		= 0x002c,	/* Flow Control Address High */
 	Fct		= 0x0030,	/* Flow Control Type */
 	Kumctrlsta	= 0x0034,	/* Kumeran Control and Status Register */
 	Connsw		= 0x0034,	/* copper / fiber switch control; 82575/82576 */
@@ -39,19 +39,22 @@
 	Fcttv		= 0x0170,	/* Flow Control Transmit Timer Value */
 	Txcw		= 0x0178,	/* Transmit Configuration Word */
 	Rxcw		= 0x0180,	/* Receive Configuration Word */
-	Ledctl		= 0x0E00,	/* LED control */
+	Ledctl		= 0x0e00,	/* LED control */
 	Pba		= 0x1000,	/* Packet Buffer Allocation */
 	Pbs		= 0x1008,	/* Packet Buffer Size */
 
 	/* Interrupt */
 
-	Icr		= 0x00C0,	/* Interrupt Cause Read */
+	Icr		= 0x00c0,	/* Interrupt Cause Read */
 	Itr		= 0x00c4,	/* Interrupt Throttling Rate */
-	Ics		= 0x00C8,	/* Interrupt Cause Set */
-	Ims		= 0x00D0,	/* Interrupt Mask Set/Read */
-	Imc		= 0x00D8,	/* Interrupt mask Clear */
-	Iam		= 0x00E0,	/* Interrupt acknowledge Auto Mask */
+	Ics		= 0x00c8,	/* Interrupt Cause Set */
+	Ims		= 0x00d0,	/* Interrupt Mask Set/Read */
+	Imc		= 0x00d8,	/* Interrupt mask Clear */
+	Iam		= 0x00e0,	/* Interrupt acknowledge Auto Mask */
+	Ivar		= 0x00e4,	/* Ivar: interrupt allocation */
 	Eitr		= 0x1680,	/* Extended itr; 82575/6 80 only */
+	P3gio		= 0x5b00,	/*  */
+	Pbaclr		= 0x5b68,	/* clear msi-x pba */
 
 	/* Receive */
 
@@ -143,6 +146,9 @@
 	Internalphy	= 0<<22,	/* " internal phy (copper) */
 	Sgmii		= 2<<22,	/* " sgmii */
 	Serdes		= 3<<22,	/* " serdes */
+	Eiame		= 1<<24,	/* extended auto mask enable */
+	Iame		= 1<<27,	/* auto mask enable */
+	Pbasup		= 1<<31,	/* msi-x pba support */
 };
 
 enum {
@@ -443,6 +449,7 @@
 	i210,
 	i217,
 	i350,
+	i354,
 	Nctlrtype,
 };
 
@@ -483,9 +490,10 @@
 	i82579,		9018,	2,	"i82579",		Fload|Fert|F79phy|Fnofct,
 	i82580,		9728,	1,	"i82580",		F75|F79phy,
 	i82583,		1514,	1,	"i82583",		0,
-	i210,		9728,	1,	"i210",		F75|F79phy|Fnofct|Fert,
+	i210,		9728,	1,	"i210",		F75|Fnofct|Fert,
 	i217,		9728,	1,	"i217",		F79phy|Fnofct|Fload|Fert,
 	i350,		9728,	1,	"i350",		F75|F79phy|Fnofct,
+	i354,		9728,	1,	"i350",		F75|F79phy|Fnofct,
 };
 
 typedef void (*Freefn)(Block*);
@@ -1417,6 +1425,7 @@
 		case i82578:
 		case i82578m:
 		case i82583:
+		case i210:
 			a = phyread(c, phyno, Phyisr) & Ane;
 			break;
 		case i82571:
@@ -1749,7 +1758,7 @@
 static int
 fload(Ctlr *c)
 {
-	uint data,  r, adr;
+	uint data, r, adr;
 	u16int sum;
 	uintmem io;
 	Flash f;
@@ -1997,6 +2006,11 @@
 	case 0x1523:		/* serdes */
 	case 0x1524:		/* sgmii */
 		return i350;
+	case 0x1f40:		/* backplane */
+	case 0x1f41:		/* sgmii */
+	case 0x1f42:		/* sgmii (c2000) */
+	case 0x1f45:		/* backplane 2.5 */
+		return i354:
 	}
 	return -1;
 }
@@ -2048,11 +2062,11 @@
 		print("%s: can't map %#P\n", cname(ctlr), ctlr->port);
 		return -1;
 	}
+	pcisetbme(p);
 	if(i82563reset(ctlr)){
 		vunmap(ctlr->nic, p->mem[0].size);
 		return -1;
 	}
-	pcisetbme(ctlr->pcidev);
 	return 0;
 }