must have 256 bytes of free space before mb->data on allocation

Reference: /n/atom/patch/applied/fs64ethalign
Date: Mon Apr 14 07:08:57 CES 2014
Signed-off-by: quanstro@quanstro.net

--- /sys/src/fs/amd64/ether82563.c	Mon Apr 14 07:08:35 2014
+++ /sys/src/fs/amd64/ether82563.c	Mon Apr 14 07:08:36 2014
@@ -32,7 +32,7 @@
 	Fla		= 0x001c,	/* Flash Access */
 	Mdic		= 0x0020,	/* MDI Control */
 	Fcal		= 0x0028,	/* Flow Control Address Low */
-	Fcah		= 0x002C,	/* Flow Control Address High */
+	Fcah		= 0x002c,	/* Flow Control Address High */
 	Fct		= 0x0030,	/* Flow Control Type */
 	Kumctrlsta	= 0x0034,	/* Kumeran Control and Status Register */
 	Connsw		= 0x0034,	/* copper / fiber switch control; 82575/82576 */
@@ -40,19 +40,22 @@
 	Fcttv		= 0x0170,	/* Flow Control Transmit Timer Value */
 	Txcw		= 0x0178,	/* Transmit Configuration Word */
 	Rxcw		= 0x0180,	/* Receive Configuration Word */
-	Ledctl		= 0x0E00,	/* LED control */
+	Ledctl		= 0x0e00,	/* LED control */
 	Pba		= 0x1000,	/* Packet Buffer Allocation */
 	Pbs		= 0x1008,	/* Packet Buffer Size */
 
 	/* Interrupt */
 
-	Icr		= 0x00C0,	/* Interrupt Cause Read */
+	Icr		= 0x00c0,	/* Interrupt Cause Read */
 	Itr		= 0x00c4,	/* Interrupt Throttling Rate */
-	Ics		= 0x00C8,	/* Interrupt Cause Set */
-	Ims		= 0x00D0,	/* Interrupt Mask Set/Read */
-	Imc		= 0x00D8,	/* Interrupt mask Clear */
-	Iam		= 0x00E0,	/* Interrupt acknowledge Auto Mask */
+	Ics		= 0x00c8,	/* Interrupt Cause Set */
+	Ims		= 0x00d0,	/* Interrupt Mask Set/Read */
+	Imc		= 0x00d8,	/* Interrupt mask Clear */
+	Iam		= 0x00e0,	/* Interrupt acknowledge Auto Mask */
+	Ivar		= 0x00e4,	/* Ivar: interrupt allocation */
 	Eitr		= 0x1680,	/* Extended itr; 82575/6 80 only */
+	P3gio		= 0x5b00,	/*  */
+	Pbaclr		= 0x5b68,	/* clear msi-x pba */
 
 	/* Receive */
 
@@ -144,6 +147,9 @@
 	Internalphy	= 0<<22,	/* " internal phy (copper) */
 	Sgmii		= 2<<22,	/* " sgmii */
 	Serdes		= 3<<22,	/* " serdes */
+	Eiame		= 1<<24,	/* extended auto mask enable */
+	Iame		= 1<<27,	/* auto mask enable */
+	Pbasup		= 1<<31,	/* msi-x pba support */
 };
 
 enum {
@@ -420,13 +426,10 @@
 	Ntd		= 256,		/* power of two */
 	Nrb		= 3*512,		/* private receive buffers per Ctlr */
 	Rbalign		= 16,		/* rx buffer alignment */
+	Mbalign		= MBALIGN,	/* actually MIN(MBALIGN, Rbalign) */
 	Npool		= 10,
 };
 
-/*
- * cavet emptor: 82577/78 have been entered speculatitively.
- * awating datasheet from intel.
- */
 enum {
 	i82563,
 	i82566,
@@ -446,6 +449,7 @@
 	i82580,
 	i82583,
 	i210,
+	i217,
 	i350,
 	Nctlrtype,
 };
@@ -457,6 +461,7 @@
 	Fpba	= 1<<3,
 	Fflashea	= 1<<4,
 	F79phy	= 1<<5,
+	Fnofct	= 1<<6,
 };
 
 typedef struct Ctlrtype Ctlrtype;
@@ -483,11 +488,12 @@
 	i82577m,		1514,	2,	"i82577",		Fload|Fert,
 	i82578,		4096,	2,	"i82578",		Fload|Fert,
 	i82578m,		1514,	2,	"i82578",		Fload|Fert,
-	i82579,		9018,	2,	"i82579",		Fload|Fert|F79phy,
+	i82579,		9018,	2,	"i82579",		Fload|Fert|F79phy|Fnofct,
 	i82580,		9728,	1,	"i82580",		F75|F79phy,
 	i82583,		1514,	1,	"i82583",		0,
-	i210,		9728,	1,	"i210",		F75|F79phy,
-	i350,		9728,	1,	"i350",		F75|F79phy,
+	i210,		9728,	1,	"i210",		F75|Fnofct|Fert,
+	i217,		9728,	1,	"i217",		F79phy|Fnofct|Fload|Fert,
+	i350,		9728,	1,	"i350",		F75|F79phy|Fnofct,
 };
 
 typedef void (*Freefn)(Block*);
@@ -714,6 +720,8 @@
 
 	p = rbtab + t;
 	b->flags |= FREE;
+	b->chan = nil;
+	b->data = (uchar*)ROUNDUP((uintptr)b->xdata, Mbalign);
 
 	ilock(p);
 	b->next = p->b;
@@ -971,8 +979,8 @@
 		ctlr->rdfree++;
 	}
 	if(i != 0){
-		sfence();
 		ctlr->rdt = rdt;
+		sfence();
 		csr32w(ctlr, Rdt, rdt);
 	}
 	return 0;
@@ -1146,6 +1154,10 @@
 		else
 			return 0;
 		return phywrite0(c, phyno, pr, p);
+	case i82576:
+	case i82577:
+	case i82578:
+		return phywrite0(c, phyno, Phy79page, p);		/* unverified */
 	case i82579:
 		return phywrite0(c, phyno, Phy79page, p<<5);
 	default:
@@ -1440,11 +1452,12 @@
 static int
 fload(Ctlr *c)
 {
-	uint data, io, r, adr;
+	uint data, r, adr;
 	u16int sum;
+	uintmem io;
 	Flash f;
 
-	io = c->pcidev->mem[1].bar & ~(uintmem)0x0f;
+	io = c->pcidev->mem[1].bar & ~(uintmem)0xf;
 	f.reg = vmap(io, c->pcidev->mem[1].size);
 	if(f.reg == nil)
 		return -1;
@@ -1522,7 +1535,7 @@
 		csr32w(ctlr, Mta + i*4, 0);
 	csr32w(ctlr, Fcal, 0x00C28001);
 	csr32w(ctlr, Fcah, 0x0100);
-	if(ctlr->type != i82579 && ctlr->type != i210 && ctlr->type != i350)
+	if((cttab[ctlr->type].flag & Fnofct) == 0)
 		csr32w(ctlr, Fct, 0x8808);
 	csr32w(ctlr, Fcttv, 0x0100);
 	csr32w(ctlr, Fcrtl, ctlr->fcrtl);
@@ -1612,13 +1625,14 @@
 	case 0x1537:		/* backplane */
 	case 0x1538:
 	case 0x1539:		/* i211 */
+		return i210;
 	case 0x153a:		/* i217-lm */
 	case 0x153b:		/* i217-v */
 	case 0x15a0:		/* i218-lm */
 	case 0x15a1:		/* i218-v */
 	case 0x15a2:		/* i218-lm */
 	case 0x15a3:		/* i218-v */
-		return i210;
+		return i217;
 	case 0x151f:		/* “powerville” eeprom-less */
 	case 0x1521:		/* copper */
 	case 0x1522:		/* fiber */
@@ -1692,11 +1706,9 @@
 int
 i82563reset(Ether *edev)
 {
-	int type;
 	Ctlr *ctlr;
 	static int done;
 
-	type = -1;
 	if(!done) {
 		i82563pci();
 		done = 1;
@@ -1710,8 +1722,6 @@
 		if(ctlr == nil)
 			return -1;
 		if(ctlr->active)
-			continue;
-		if(type != -1 && ctlr->type != type)
 			continue;
 		if(ethercfgmatch(edev, ctlr->pcidev, ctlr->port) == 0){
 			ctlr->active = 1;
--- /sys/src/fs/amd64/ether82598.c	Mon Apr 14 07:08:38 2014
+++ /sys/src/fs/amd64/ether82598.c	Mon Apr 14 07:08:40 2014
@@ -315,6 +315,7 @@
 	Nrb	= 2048,
 	Nctlr	= 8,
 	Rbalign	= 8,		/* ideally, 4k */
+	Mbalign	= MBALIGN,	/* actually MIN(MBALIGN, Rbalign) */
 };
 
 static	Ctlr	*ctlrtab[Nctlr];
@@ -386,7 +387,7 @@
 	Rbpool *p;
 
 	p = rbtab + t;
-	b->data = (uchar*)ROUNDUP((uintptr)b->xdata, Rbalign);
+	b->data = (uchar*)ROUNDUP((uintptr)b->xdata, Mbalign);
 	b->count = 0;
 	b->flags = FREE;