whitespace patches for emmc.c Reference: /n/atom/patch/applied/emmcws Date: Sun Jan 10 18:37:06 CET 2016 Signed-off-by: quanstro@quanstro.net --- /sys/src/9/bcm/emmc.c Sun Jan 10 18:36:57 2016 +++ /sys/src/9/bcm/emmc.c Sun Jan 10 18:36:58 2016 @@ -1,3 +1,9 @@ +/* + * bcm2835 external mass media controller (mmc / sd host interface) + * + * Copyright © 2012 Richard Miller + */ + #include "u.h" #include "../port/lib.h" #include "../port/error.h" @@ -7,28 +13,21 @@ #include "io.h" #include "../port/sd.h" -/* - * bcm2835 external mass media controller (mmc / sd host interface) - * - * Copyright © 2012 Richard Miller - * - */ - #define EMMCREGS (VIRTIO+0x300000) enum { - Extfreq = 100*Mhz, /* guess external clock frequency if - not available from vcore */ - Initfreq = 400000, /* initialisation frequency for MMC */ - SDfreq = 25*Mhz, /* standard SD frequency */ - DTO = 14, /* data timeout exponent (guesswork) */ + Extfreq = 100*Mhz, /* guess external clock frequency if */ + /* not available from vcore */ + Initfreq = 400000, /* initialisation frequency for MMC */ + SDfreq = 25*Mhz, /* standard SD frequency */ + DTO = 14, /* data timeout exponent (guesswork) */ - MMCSelect = 7, /* mmc/sd card select command */ - Setbuswidth = 6, /* mmc/sd set bus width command */ + MMCSelect = 7, /* mmc/sd card select command */ + Setbuswidth = 6, /* mmc/sd set bus width command */ }; enum { -/* Controller registers */ + /* Controller registers */ Arg2 = 0x00>>2, Blksizecnt = 0x04>>2, Arg1 = 0x08>>2, @@ -51,32 +50,32 @@ Exrdfifocfg = 0x80>>2, Exrdfifoen = 0x84>>2, Tunestep = 0x88>>2, - Tunestepsstd = 0x8c>>2, - Tunestepsddr = 0x90>>2, + Tunestepsstd = 0x8c>>2, + Tunestepsddr = 0x90>>2, Spiintspt = 0xf0>>2, Slotisrver = 0xfc>>2, -/* Control0 */ + /* Control0 */ Dwidth4 = 1<<1, Dwidth1 = 0<<1, -/* Control1 */ + /* Control1 */ Srstdata = 1<<26, /* reset data circuit */ Srstcmd = 1<<25, /* reset command circuit */ Srsthc = 1<<24, /* reset complete host controller */ - Datatoshift = 16, /* data timeout unit exponent */ - Datatomask = 0xF0000, - Clkfreq8shift = 8, /* SD clock base divider LSBs */ + Datatoshift = 16, /* data timeout unit exponent */ + Datatomask = 0xF0000, + Clkfreq8shift = 8, /* SD clock base divider LSBs */ Clkfreq8mask = 0xFF00, - Clkfreqms2shift = 6, /* SD clock base divider MSBs */ + Clkfreqms2shift = 6, /* SD clock base divider MSBs */ Clkfreqms2mask = 0xC0, Clkgendiv = 0<<5, /* SD clock divided */ Clkgenprog = 1<<5, /* SD clock programmable */ Clken = 1<<2, /* SD clock enable */ Clkstable = 1<<1, - Clkintlen = 1<<0, /* clock enable for internal EMMC clocks */ + Clkintlen = 1<<0, /* enable internal EMMC clocks */ -/* Cmdtm */ + /* Cmdtm */ Indexshift = 24, Suspend = 1<<22, Resume = 2<<22, @@ -96,7 +95,7 @@ Autocmd23 = 2<<2, Blkcnten = 1<<1, -/* Interrupt */ + /* Interrupt */ Acmderr = 1<<24, Denderr = 1<<22, Dcrcerr = 1<<21, @@ -105,7 +104,7 @@ Cenderr = 1<<18, Ccrcerr = 1<<17, Ctoerr = 1<<16, - Err = 1<<15, + Err = 1<<15, Cardintr = 1<<8, /* not in Broadcom datasheet */ Cardinsert = 1<<6, /* not in Broadcom datasheet */ Readrdy = 1<<5, @@ -113,7 +112,7 @@ Datadone = 1<<1, Cmddone = 1<<0, -/* Status */ + /* Status */ Bufread = 1<<11, /* not in Broadcom datasheet */ Bufwrite = 1<<10, /* not in Broadcom datasheet */ Readtrans = 1<<9, @@ -146,8 +145,8 @@ struct Ctlr { Rendez r; - int datadone; - int fastclock; + int datadone; + int fastclock; ulong extclk; }; @@ -171,15 +170,19 @@ uint v; assert(d < 1<<10); - v = (d<>8)<> 8) << Clkfreqms2shift) & Clkfreqms2mask; return v; } static int datadone(void*) { - return emmc.datadone; + int i; + + u32int *r = (u32int*)EMMCREGS; + i = r[Interrupt]; + return i & (Datadone|Err); } static int @@ -198,10 +201,11 @@ emmc.extclk = clk; print("%seMMC external clock %lud Mhz\n", s, clk/1000000); r = (u32int*)EMMCREGS; - if(0)print("emmc control %8.8ux %8.8ux %8.8ux\n", r[Control0], r[Control1], r[Control2]); + if(0)print("emmc control %8.8ux %8.8ux %8.8ux\n", + r[Control0], r[Control1], r[Control2]); WR(Control1, Srsthc); delay(10); - while(r[Control1]&Srsthc) + while(r[Control1] & Srsthc) ; return 0; } @@ -213,7 +217,7 @@ uint ver; r = (u32int*)EMMCREGS; - ver = r[Slotisrver]>>16; + ver = r[Slotisrver] >> 16; return snprint(inquiry, inqlen, "Arasan eMMC SD Host Controller %2.2x Version %2.2x", ver&0xFF, ver>>8); @@ -226,8 +230,8 @@ int i; r = (u32int*)EMMCREGS; - WR(Control1, clkdiv(emmc.extclk/Initfreq-1) | - DTO<>24 | r[Resp1]<<8; @@ -303,17 +309,19 @@ break; case Respnone: resp[0] = 0; + break; } - if((c&Respmask) == Resp48busy){ + if((c & Respmask) == Resp48busy){ WR(Irpten, Datadone|Err); tsleep(&emmc.r, datadone, 0, 3000); - i = emmc.datadone; - emmc.datadone = 0; WR(Irpten, 0); - if((i&Datadone) == 0) + emmc.datadone = 0; + i = r[Interrupt]; + if((i & Datadone) == 0) print("emmcio: no Datadone after CMD%d\n", cmd); - if(i&Err) - print("emmcio: CMD%d error interrupt %ux\n", cmd, r[Interrupt]); + if(i & Err) + print("emmcio: CMD%d error interrupt %ux\n", + cmd, r[Interrupt]); WR(Interrupt, i); } /* @@ -321,8 +329,8 @@ */ if(cmd == MMCSelect){ delay(10); - WR(Control1, clkdiv(emmc.extclk/SDfreq-1) | - DTO<